diff options
| author | Samuel Pitoiset <[email protected]> | 2018-04-06 15:37:28 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-04-09 11:21:10 +0200 |
| commit | 0fc9113ac593e396d3b103bebb2713aac9d072ff (patch) | |
| tree | 21c03ba72739d46d99c46375975e71cd7ee07260 /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | 32f5174ce825d13ed3b1cb6e8c5f8091ddc5045f (diff) | |
radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpers
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7003818b5b5..e8a6d9be155 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -947,7 +947,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, va += image->offset + image->clear_value_offset; unsigned reg_offset = 0, reg_count = 0; - assert(image->surface.htile_size); + assert(radv_image_has_htile(image)); if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { ++reg_count; @@ -985,7 +985,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, va += image->offset + image->clear_value_offset; unsigned reg_offset = 0, reg_count = 0; - if (!image->surface.htile_size) + if (!radv_image_has_htile(image)) return; if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { @@ -1024,7 +1024,7 @@ radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->dcc_pred_offset; - assert(image->surface.dcc_size); + assert(radv_image_has_dcc(image)); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | @@ -1045,7 +1045,7 @@ radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; - assert(image->cmask.size || image->surface.dcc_size); + assert(radv_image_has_cmask(image) || radv_image_has_dcc(image)); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | @@ -1069,7 +1069,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; - if (!image->cmask.size && !image->surface.dcc_size) + if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image)) return; uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c; @@ -3631,7 +3631,7 @@ static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffe const VkImageSubresourceRange *range) { if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { - if (image->fmask.size) + if (radv_image_has_fmask(image)) radv_initialise_cmask(cmd_buffer, image, 0xccccccccu); else radv_initialise_cmask(cmd_buffer, image, 0xffffffffu); @@ -3707,18 +3707,18 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index); unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index); - if (image->surface.htile_size) + if (radv_image_has_htile(image)) radv_handle_depth_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range, pending_clears); - if (image->cmask.size || image->fmask.size) + if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) radv_handle_cmask_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range); - if (image->surface.dcc_size) + if (radv_image_has_dcc(image)) radv_handle_dcc_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range); |