diff options
author | Marek Olšák <[email protected]> | 2019-11-22 17:41:22 -0500 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2019-11-25 16:48:27 -0500 |
commit | f671cc4d95eaf9ecfaafb216afeff7dc89f66cbf (patch) | |
tree | 4309fd0c0e64d959d27072d7c33236de37e062fa /src/amd/llvm | |
parent | 8afab607ac37871771cd75ac9dfdaea3bea65d25 (diff) |
ac: set swizzled bit in cache policy as a hint not to merge loads/stores
LLVM now merges loads and stores for all opcodes, so this must be set.
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/llvm')
-rw-r--r-- | src/amd/llvm/ac_llvm_build.c | 11 | ||||
-rw-r--r-- | src/amd/llvm/ac_llvm_build.h | 4 | ||||
-rw-r--r-- | src/amd/llvm/ac_nir_to_llvm.c | 2 |
3 files changed, 7 insertions, 10 deletions
diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index 35472900e98..60213fdd5d7 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -1237,8 +1237,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx, LLVMValueRef voffset, LLVMValueRef soffset, unsigned inst_offset, - unsigned cache_policy, - bool swizzle_enable_hint) + unsigned cache_policy) { /* Split 3 channel stores, because only LLVM 9+ support 3-channel * intrinsics. */ @@ -1252,12 +1251,10 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx, v01 = ac_build_gather_values(ctx, v, 2); ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset, - soffset, inst_offset, cache_policy, - swizzle_enable_hint); + soffset, inst_offset, cache_policy); ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset, soffset, inst_offset + 8, - cache_policy, - swizzle_enable_hint); + cache_policy); return; } @@ -1265,7 +1262,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx, * (voffset is swizzled, but soffset isn't swizzled). * llvm.amdgcn.buffer.store doesn't have a separate soffset parameter. */ - if (!swizzle_enable_hint) { + if (!(cache_policy & ac_swizzled)) { LLVMValueRef offset = soffset; if (inst_offset) diff --git a/src/amd/llvm/ac_llvm_build.h b/src/amd/llvm/ac_llvm_build.h index 2357e42035c..8f6d56ab687 100644 --- a/src/amd/llvm/ac_llvm_build.h +++ b/src/amd/llvm/ac_llvm_build.h @@ -299,8 +299,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx, LLVMValueRef voffset, LLVMValueRef soffset, unsigned inst_offset, - unsigned cache_policy, - bool swizzle_enable_hint); + unsigned cache_policy); void ac_build_buffer_store_format(struct ac_llvm_context *ctx, @@ -533,6 +532,7 @@ enum ac_image_cache_policy { ac_glc = 1 << 0, /* per-CU cache control */ ac_slc = 1 << 1, /* global L2 cache control */ ac_dlc = 1 << 2, /* per-shader-array cache control */ + ac_swizzled = 1 << 3, /* the access is swizzled, disabling load/store merging */ }; struct ac_image_args { diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 9e9ddf62555..2eba80a9c38 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -1650,7 +1650,7 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, ac_build_buffer_store_dword(&ctx->ac, rsrc, data, num_channels, offset, ctx->ac.i32_0, 0, - cache_policy, false); + cache_policy); } } } |