diff options
| author | Rhys Perry <[email protected]> | 2020-04-24 00:21:46 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-04-24 08:55:19 +0000 |
| commit | 665250e8300e2b0f3eae27628a9a6f2666e650dd (patch) | |
| tree | a488d7d1f2f916c518622783e38a09e5aad8e127 /src/amd/compiler/aco_optimizer.cpp | |
| parent | 58b8fbb824f22ed7009747bdab23b919966a8d7a (diff) | |
aco: fix v_or(s_lshl) and v_add(s_lshl) optimizations
Signed-off-by: Rhys Perry <[email protected]>
Fixes: d1621834f367d41500b7c1a819c046eb429fb8a6
('aco: combine VALU and SALU into various VOP3 instructions')
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2822
Reviewed-by: Timur Kristóf <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4717>
Diffstat (limited to 'src/amd/compiler/aco_optimizer.cpp')
| -rw-r--r-- | src/amd/compiler/aco_optimizer.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 0b4729e512d..7c9eb3e1100 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -2475,7 +2475,7 @@ void combine_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr else if (combine_three_valu_op(ctx, instr, aco_opcode::v_or_b32, aco_opcode::v_or3_b32, "012", 1 | 2)) ; else if (combine_three_valu_op(ctx, instr, aco_opcode::s_and_b32, aco_opcode::v_and_or_b32, "120", 1 | 2)) ; else if (combine_three_valu_op(ctx, instr, aco_opcode::v_and_b32, aco_opcode::v_and_or_b32, "120", 1 | 2)) ; - else if (combine_three_valu_op(ctx, instr, aco_opcode::s_lshl_b32, aco_opcode::v_lshl_or_b32, "201", 1 | 2)) ; + else if (combine_three_valu_op(ctx, instr, aco_opcode::s_lshl_b32, aco_opcode::v_lshl_or_b32, "120", 1 | 2)) ; else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_or_b32, "210", 1 | 2); } else if (instr->opcode == aco_opcode::v_add_u32 && ctx.program->chip_class >= GFX9) { if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) ; @@ -2483,7 +2483,7 @@ void combine_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr else if (combine_three_valu_op(ctx, instr, aco_opcode::s_add_i32, aco_opcode::v_add3_u32, "012", 1 | 2)) ; else if (combine_three_valu_op(ctx, instr, aco_opcode::s_add_u32, aco_opcode::v_add3_u32, "012", 1 | 2)) ; else if (combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add3_u32, "012", 1 | 2)) ; - else if (combine_three_valu_op(ctx, instr, aco_opcode::s_lshl_b32, aco_opcode::v_lshl_add_u32, "201", 1 | 2)) ; + else if (combine_three_valu_op(ctx, instr, aco_opcode::s_lshl_b32, aco_opcode::v_lshl_add_u32, "120", 1 | 2)) ; else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_add_u32, "210", 1 | 2); } else if (instr->opcode == aco_opcode::v_lshlrev_b32 && ctx.program->chip_class >= GFX9) { combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add_lshl_u32, "120", 2); |