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authorMarek Olšák <[email protected]>2019-09-03 22:38:38 -0400
committerMarek Olšák <[email protected]>2019-12-16 17:04:57 -0500
commit69ea473eeb91b2c4db26402c3bc2ed5799d26605 (patch)
tree4294bf82e95f2425cfc8d40c9b5d5ac53249f1cb /src/amd/common
parenta3ea4805aad2bfbd572c01ba1e982b69e00f6d07 (diff)
amd/addrlib: update to the latest version
Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Diffstat (limited to 'src/amd/common')
-rw-r--r--src/amd/common/ac_surface.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 016590fc085..09f2bb75ea0 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -85,7 +85,6 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
if (addrCreateInput.chipFamily >= FAMILY_AI) {
addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
- regValue.blockVarSizeLog2 = 0;
} else {
regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
@@ -1599,11 +1598,9 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
case ADDR_SW_256B_S:
case ADDR_SW_4KB_S:
case ADDR_SW_64KB_S:
- case ADDR_SW_VAR_S:
case ADDR_SW_64KB_S_T:
case ADDR_SW_4KB_S_X:
case ADDR_SW_64KB_S_X:
- case ADDR_SW_VAR_S_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
break;
@@ -1612,11 +1609,9 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
case ADDR_SW_256B_D:
case ADDR_SW_4KB_D:
case ADDR_SW_64KB_D:
- case ADDR_SW_VAR_D:
case ADDR_SW_64KB_D_T:
case ADDR_SW_4KB_D_X:
case ADDR_SW_64KB_D_X:
- case ADDR_SW_VAR_D_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
break;
@@ -1624,7 +1619,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
case ADDR_SW_256B_R:
case ADDR_SW_4KB_R:
case ADDR_SW_64KB_R:
- case ADDR_SW_VAR_R:
case ADDR_SW_64KB_R_T:
case ADDR_SW_4KB_R_X:
case ADDR_SW_64KB_R_X:
@@ -1641,7 +1635,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
/* Z = depth. */
case ADDR_SW_4KB_Z:
case ADDR_SW_64KB_Z:
- case ADDR_SW_VAR_Z:
case ADDR_SW_64KB_Z_T:
case ADDR_SW_4KB_Z_X:
case ADDR_SW_64KB_Z_X: