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authorMarek Olšák <[email protected]>2018-04-30 20:54:06 -0400
committerMarek Olšák <[email protected]>2018-05-10 18:26:33 -0400
commit9bf3570fed064cfc5a863fa4bd4802f11b1030f5 (patch)
tree11b511fce9e43f01b9ccf8ecdd31b0e46d8822ab /src/amd/common/ac_surface.h
parent276acda835a8b7e12ff84012c58e776a12e83769 (diff)
ac/surface/gfx6: compute FMASK together with the color surface
instead of invoking FMASK computation separately. Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd/common/ac_surface.h')
-rw-r--r--src/amd/common/ac_surface.h13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 37df859e6de..d0249684ad2 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -79,6 +79,16 @@ struct legacy_surf_level {
enum radeon_surf_mode mode:2;
};
+struct legacy_surf_fmask {
+ uint64_t size;
+ unsigned alignment;
+ unsigned tile_swizzle;
+ unsigned slice_tile_max; /* max 4M */
+ uint8_t tiling_index; /* max 31 */
+ uint8_t bankh; /* max 8 */
+ uint16_t pitch_in_pixels;
+};
+
struct legacy_surf_layout {
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
@@ -101,6 +111,7 @@ struct legacy_surf_layout {
struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
+ struct legacy_surf_fmask fmask;
};
/* Same as addrlib - AddrResourceType. */
@@ -222,7 +233,7 @@ struct ac_surf_info {
uint8_t num_channels; /* heuristic for displayability */
uint16_t array_size;
uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
- uint32_t *fmask_surf_index; /* GFX9+ */
+ uint32_t *fmask_surf_index;
};
struct ac_surf_config {