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| author | Samuel Pitoiset <[email protected]> | 2019-08-02 12:10:43 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:05 +0200 |
| commit | d62d2840c42d0eb3433c6c0c8bfe8d506c0475b9 (patch) | |
| tree | 15dc1af10891dce96f59d2881de6c3e1999a8cdd /src/amd/common/ac_gpu_info.h | |
| parent | af65f9431e0fea5df0957987efeb0b87cee6cadc (diff) | |
ac: add has_clear_state to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/common/ac_gpu_info.h')
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 8418a62e387..69bac7252bf 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -58,6 +58,7 @@ struct radeon_info { uint32_t num_sdma_rings; uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + bool has_clear_state; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ |