diff options
| author | Nicolai Hähnle <[email protected]> | 2016-07-20 21:30:56 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | fbc9ba7559b15d29cd8dc38dfb3751845ef3fd37 (patch) | |
| tree | a2f41c4e5870de65a0328f0cda3061dc98156c34 /src/amd/addrlib/core | |
| parent | 145750efba609bc03d6216f9e08fed18bf3a1498 (diff) | |
amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
Diffstat (limited to 'src/amd/addrlib/core')
| -rw-r--r-- | src/amd/addrlib/core/addrlib1.cpp | 12 | ||||
| -rw-r--r-- | src/amd/addrlib/core/addrlib1.h | 10 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp index d48aa7c92bf..040891c431c 100644 --- a/src/amd/addrlib/core/addrlib1.cpp +++ b/src/amd/addrlib/core/addrlib1.cpp @@ -3228,13 +3228,14 @@ VOID Lib::PadDimensions( UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3 UINT_32 mipLevel, ///< [in] MipLevel UINT_32* pPitch, ///< [in,out] pitch in pixels - UINT_32 pitchAlign, ///< [in] pitch alignment + UINT_32* pPitchAlign, ///< [in,out] pitch align could be changed in HwlPadDimensions UINT_32* pHeight, ///< [in,out] height in pixels UINT_32 heightAlign, ///< [in] height alignment UINT_32* pSlices, ///< [in,out] number of slices UINT_32 sliceAlign ///< [in] number of slice alignment ) const { + UINT_32 pitchAlign = *pPitchAlign; UINT_32 thickness = Thickness(tileMode); ADDR_ASSERT(padDims <= 3); @@ -3302,14 +3303,11 @@ VOID Lib::PadDimensions( flags, numSamples, pTileInfo, - padDims, mipLevel, pPitch, - pitchAlign, - pHeight, - heightAlign, - pSlices, - sliceAlign); + pPitchAlign, + *pHeight, + heightAlign); } diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h index 9c66f53e737..c1fc693b64f 100644 --- a/src/amd/addrlib/core/addrlib1.h +++ b/src/amd/addrlib/core/addrlib1.h @@ -71,6 +71,9 @@ struct TileModeFlags UINT_32 isBankSwapped : 1; }; +static const UINT_32 Block64K = 0x10000; +static const UINT_32 PrtTileSize = Block64K; + /** **************************************************************************************************** * @brief This class contains asic independent address lib functionalities @@ -365,14 +368,13 @@ protected: VOID PadDimensions( AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, - UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign, + UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32* pHeight, UINT_32 heightAlign, UINT_32* pSlices, UINT_32 sliceAlign) const; virtual VOID HwlPadDimensions( AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, - UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, - UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign, - UINT_32* pSlices, UINT_32 sliceAlign) const + UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel, + UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32 height, UINT_32 heightAlign) const { } |