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authorXiaoYuan Zheng <[email protected]>2015-01-22 05:08:05 -0500
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commit6164f23a9140ae8dfa4d44f7a9c41228e36fa9bf (patch)
treeb6abcb2c539b28e7a5ae345cac957df992270bda /src/amd/addrlib/addrinterface.h
parent3bd1380ab2aea14d6187110982b8ba576eefb073 (diff)
amdgpu/addrlib: add tcCompatible htile addr from coordinate support.
Diffstat (limited to 'src/amd/addrlib/addrinterface.h')
-rw-r--r--src/amd/addrlib/addrinterface.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index 01d8788f4b8..079596767e2 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -851,6 +851,7 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
UINT_32 slice; ///< Index of slice
UINT_32 numSlices; ///< Number of slices
BOOL_32 isLinear; ///< Linear or tiled HTILE layout
+ ADDR_HTILE_FLAGS flags; ///< htile flags
AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
ADDR_TILEINFO* pTileInfo; ///< Tile info
@@ -859,6 +860,8 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
/// while the global useTileIndex is set to 1
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
///< README: When tileIndex is not -1, this must be valid
+ UINT_32 bpp; ///< depth/stencil buffer bit per pixel size
+ UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address
} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
/**