intel/isl: Move isl_calc_array_pitch_el_rows higher up

Reviewed-by: Topi Pohjolainen <[email protected]>

1 files changed, 117 insertions, 117 deletions

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f0e948a1c96..b573f0d9973 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -712,6 +712,123 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
 }
 
 /**
+ * Calculate the pitch between physical array slices, in units of rows of
+ * surface elements.
+ */
+static uint32_t
+isl_calc_array_pitch_el_rows(const struct isl_device *dev,
+                             const struct isl_surf_init_info *restrict info,
+                             const struct isl_tile_info *tile_info,
+                             enum isl_dim_layout dim_layout,
+                             enum isl_array_pitch_span array_pitch_span,
+                             const struct isl_extent3d *image_align_sa,
+                             const struct isl_extent4d *phys_level0_sa,
+                             const struct isl_extent2d *phys_slice0_sa)
+{
+   const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+   uint32_t pitch_sa_rows = 0;
+
+   switch (dim_layout) {
+   case ISL_DIM_LAYOUT_GEN9_1D:
+      /* Each row is an array slice */
+      pitch_sa_rows = 1;
+      break;
+   case ISL_DIM_LAYOUT_GEN4_2D:
+      switch (array_pitch_span) {
+      case ISL_ARRAY_PITCH_SPAN_COMPACT:
+         pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
+         break;
+      case ISL_ARRAY_PITCH_SPAN_FULL: {
+         /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
+          * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
+          * Surfaces >> Surface Arrays.
+          */
+         uint32_t H0_sa = phys_level0_sa->h;
+         uint32_t H1_sa = isl_minify(H0_sa, 1);
+
+         uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
+         uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
+
+         uint32_t m;
+         if (ISL_DEV_GEN(dev) >= 7) {
+            /* The QPitch equation changed slightly in Ivybridge. */
+            m = 12;
+         } else {
+            m = 11;
+         }
+
+         pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
+
+         if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
+             (info->height % 4 == 1)) {
+            /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
+             * Graphics Core >> Section 7.18.3.7: Surface Arrays:
+             *
+             *    [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
+             *    the value calculated in the equation above , for every
+             *    other odd Surface Height starting from 1 i.e. 1,5,9,13.
+             *
+             * XXX(chadv): Is the errata natural corollary of the physical
+             * layout of interleaved samples?
+             */
+            pitch_sa_rows += 4;
+         }
+
+         pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
+         } /* end case */
+         break;
+      }
+      break;
+   case ISL_DIM_LAYOUT_GEN4_3D:
+      assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
+      pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
+      break;
+   default:
+      unreachable("bad isl_dim_layout");
+      break;
+   }
+
+   assert(pitch_sa_rows % fmtl->bh == 0);
+   uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
+
+   if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
+      /*
+       * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
+       *
+       *    "Mip-mapped and arrayed surfaces are supported with MCS buffer
+       *    layout with these alignments in the RT space: Horizontal
+       *    Alignment = 128 and Vertical Alignment = 64."
+       *
+       * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
+       *
+       *    "For non-multisampled render target's CCS auxiliary surface,
+       *    QPitch must be computed with Horizontal Alignment = 128 and
+       *    Surface Vertical Alignment = 256. These alignments are only for
+       *    CCS buffer and not for associated render target."
+       *
+       * The first restriction is already handled by isl_choose_image_alignment_el
+       * but the second restriction, which is an extension of the first, only
+       * applies to qpitch and must be applied here.
+       */
+      assert(fmtl->bh == 4);
+      pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
+   }
+
+   if (ISL_DEV_GEN(dev) >= 9 &&
+       info->dim == ISL_SURF_DIM_3D &&
+       tile_info->tiling != ISL_TILING_LINEAR) {
+      /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
+       *
+       *    Tile Mode != Linear: This field must be set to an integer multiple
+       *    of the tile height
+       */
+      pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
+   }
+
+   return pitch_el_rows;
+}
+
+/**
  * A variant of isl_calc_phys_slice0_extent_sa() specific to
  * ISL_DIM_LAYOUT_GEN4_2D.
  */
@@ -891,123 +1008,6 @@ isl_calc_phys_slice0_extent_sa(const struct isl_device *dev,
    }
 }
 
-/**
- * Calculate the pitch between physical array slices, in units of rows of
- * surface elements.
- */
-static uint32_t
-isl_calc_array_pitch_el_rows(const struct isl_device *dev,
-                             const struct isl_surf_init_info *restrict info,
-                             const struct isl_tile_info *tile_info,
-                             enum isl_dim_layout dim_layout,
-                             enum isl_array_pitch_span array_pitch_span,
-                             const struct isl_extent3d *image_align_sa,
-                             const struct isl_extent4d *phys_level0_sa,
-                             const struct isl_extent2d *phys_slice0_sa)
-{
-   const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-   uint32_t pitch_sa_rows = 0;
-
-   switch (dim_layout) {
-   case ISL_DIM_LAYOUT_GEN9_1D:
-      /* Each row is an array slice */
-      pitch_sa_rows = 1;
-      break;
-   case ISL_DIM_LAYOUT_GEN4_2D:
-      switch (array_pitch_span) {
-      case ISL_ARRAY_PITCH_SPAN_COMPACT:
-         pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
-         break;
-      case ISL_ARRAY_PITCH_SPAN_FULL: {
-         /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
-          * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
-          * Surfaces >> Surface Arrays.
-          */
-         uint32_t H0_sa = phys_level0_sa->h;
-         uint32_t H1_sa = isl_minify(H0_sa, 1);
-
-         uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
-         uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
-
-         uint32_t m;
-         if (ISL_DEV_GEN(dev) >= 7) {
-            /* The QPitch equation changed slightly in Ivybridge. */
-            m = 12;
-         } else {
-            m = 11;
-         }
-
-         pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
-
-         if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
-             (info->height % 4 == 1)) {
-            /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
-             * Graphics Core >> Section 7.18.3.7: Surface Arrays:
-             *
-             *    [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
-             *    the value calculated in the equation above , for every
-             *    other odd Surface Height starting from 1 i.e. 1,5,9,13.
-             *
-             * XXX(chadv): Is the errata natural corollary of the physical
-             * layout of interleaved samples?
-             */
-            pitch_sa_rows += 4;
-         }
-
-         pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
-         } /* end case */
-         break;
-      }
-      break;
-   case ISL_DIM_LAYOUT_GEN4_3D:
-      assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
-      pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
-      break;
-   default:
-      unreachable("bad isl_dim_layout");
-      break;
-   }
-
-   assert(pitch_sa_rows % fmtl->bh == 0);
-   uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
-
-   if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
-      /*
-       * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
-       *
-       *    "Mip-mapped and arrayed surfaces are supported with MCS buffer
-       *    layout with these alignments in the RT space: Horizontal
-       *    Alignment = 128 and Vertical Alignment = 64."
-       *
-       * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
-       *
-       *    "For non-multisampled render target's CCS auxiliary surface,
-       *    QPitch must be computed with Horizontal Alignment = 128 and
-       *    Surface Vertical Alignment = 256. These alignments are only for
-       *    CCS buffer and not for associated render target."
-       *
-       * The first restriction is already handled by isl_choose_image_alignment_el
-       * but the second restriction, which is an extension of the first, only
-       * applies to qpitch and must be applied here.
-       */
-      assert(fmtl->bh == 4);
-      pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
-   }
-
-   if (ISL_DEV_GEN(dev) >= 9 &&
-       info->dim == ISL_SURF_DIM_3D &&
-       tile_info->tiling != ISL_TILING_LINEAR) {
-      /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
-       *
-       *    Tile Mode != Linear: This field must be set to an integer multiple
-       *    of the tile height
-       */
-      pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
-   }
-
-   return pitch_el_rows;
-}
-
 static uint32_t
 isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
                              const struct isl_tile_info *tile_info)