diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2019-10-18 01:21:29 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-10-18 10:49:29 +0000 |
| commit | fd21ee8b52fb9416b16c63fd34c699b1301ce30c (patch) | |
| tree | 1fefcc2547ac485b25a30803105c2661f9c013b4 | |
| parent | 1b65c49c58c8a3d6a7b4a35a6e5c8f96d1828c23 (diff) | |
radv: Fix single stage constant flush with merged shaders.
e.g. a VERTEX only flush with tess on Vega should look at the TCS
to see which bits are needed.
CC: <[email protected]>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1953
Reviewed-by: Samuel Pitoiset <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1e5e2834135..01a0787dcf5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2313,14 +2313,15 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, return; radv_foreach_stage(stage, stages) { - if (!pipeline->shaders[stage]) + shader = radv_get_shader(pipeline, stage); + if (!shader) continue; - need_push_constants |= pipeline->shaders[stage]->info.loads_push_constants; - need_push_constants |= pipeline->shaders[stage]->info.loads_dynamic_offsets; + need_push_constants |= shader->info.loads_push_constants; + need_push_constants |= shader->info.loads_dynamic_offsets; - uint8_t base = pipeline->shaders[stage]->info.base_inline_push_consts; - uint8_t count = pipeline->shaders[stage]->info.num_inline_push_consts; + uint8_t base = shader->info.base_inline_push_consts; + uint8_t count = shader->info.num_inline_push_consts; radv_emit_inline_push_consts(cmd_buffer, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS, |