diff options
| author | Tom Stellard <[email protected]> | 2012-08-31 16:11:38 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-09-04 14:21:10 -0400 |
| commit | f9fede884b7ace711ccf63152afdbdaf209edced (patch) | |
| tree | f6a299809e87115eb037e3a85da382bc3a13c34c | |
| parent | f73ffacbf0c65ad843406af37aa35e9112bc8038 (diff) | |
radeon/llvm: Fix encoding of V_CNDMASK_B32
The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register. This has been fixed by moving the VCC
register to the end of the operand list.
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.cpp | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp index d2fd995ad01..a64e2a378ff 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.cpp +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp @@ -242,9 +242,9 @@ void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32)) .addOperand(MI->getOperand(0)) - .addReg(AMDGPU::VCC) .addOperand(MI->getOperand(2)) - .addOperand(MI->getOperand(3)); + .addOperand(MI->getOperand(3)) + .addReg(AMDGPU::VCC); MI->eraseFromParent(); } diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 291c03418a0..e9e91fda58a 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -670,7 +670,7 @@ def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16", /* XXX: No VOP3 version of this instruction yet */ def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst), - (ins VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1), "V_CNDMASK_B32", + (ins AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc), "V_CNDMASK_B32", [(set (i32 VReg_32:$dst), (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > { @@ -680,7 +680,7 @@ def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst), //f32 pattern for V_CNDMASK_B32 def : Pat < (f32 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)), - (V_CNDMASK_B32 VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1) + (V_CNDMASK_B32 AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc) >; defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; |