diff options
| author | Jordan Justen <[email protected]> | 2020-01-16 13:16:24 -0800 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-28 21:57:17 +0000 |
| commit | da03e07cc2f09b451705eeadfb24a12a640f6961 (patch) | |
| tree | e13959433725dab6bd548add924a8a6f053a645a | |
| parent | b175effc7252f9e73dd78dfac0380cae69966234 (diff) | |
iris: Emit CS Stall before Instruction Cache flush for gen12 WA
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.
Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 5fbb24bdf7f..1b856335f61 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6848,6 +6848,18 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, 0, NULL, 0, 0); } + /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which + * invalidates the instruction cache + */ + if (GEN_GEN == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) { + iris_emit_raw_pipe_control(batch, + "workaround: CS stall before instruction " + "cache invalidate", + PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset, + imm); + } + if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * |