freedreno/regs: update a6xx PC regs

Update some registers in the 0x9800-0xa000 range.

Signed-off-by: Jonathan Marek <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5870>

6 files changed, 61 insertions, 55 deletions

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index b03bd3f327c..63e8e01058f 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1592,16 +1592,6 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
 	<reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
 	<reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
-	<reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
-	<reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
-	<reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
-	<reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
-	<reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
-	<reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
-	<reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
-	<reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
-	<reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
-	<reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
 	<reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
 	<reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
 	<reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
@@ -2767,41 +2757,41 @@ to upconvert to 32b float internally?
 	<!-- TODO: regs from 0x9624-0x963a -->
 	<!-- 0x963b-0x97ff invalid -->
 
-	<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
+	<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
 
 	<!-- always 0x0 ? -->
-	<reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
+	<reg32 offset="0x9801" name="PC_UNKNOWN_9801">
+		<bitfield name="UNK0" low="0" high="10"/>
+		<bitfield name="UNK13" pos="13"/>
+	</reg32>
 
 	<enum name="a6xx_tess_spacing">
-	  <value value="0x0" name="TESS_EQUAL"/>
-	  <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
-	  <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
+		<value value="0x0" name="TESS_EQUAL"/>
+		<value value="0x2" name="TESS_FRACTIONAL_ODD"/>
+		<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
 	</enum>
-
 	<enum name="a6xx_tess_output">
-	  <value value="0x0" name="TESS_POINTS"/>
-	  <value value="0x1" name="TESS_LINES"/>
-	  <value value="0x2" name="TESS_CW_TRIS"/>
-	  <value value="0x3" name="TESS_CCW_TRIS"/>
+		<value value="0x0" name="TESS_POINTS"/>
+		<value value="0x1" name="TESS_LINES"/>
+		<value value="0x2" name="TESS_CW_TRIS"/>
+		<value value="0x3" name="TESS_CCW_TRIS"/>
 	</enum>
-
 	<reg32 offset="0x9802" name="PC_TESS_CNTL">
-	  <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
-	  <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
+		<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
+		<bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
 	</reg32>
 
-	<!-- probably: -->
-	<reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
-	<reg32 offset="0x9804" name="PC_MODE_CNTL"/>
+	<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
+	<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
 
 	<!-- always 0x1 ? -->
-	<reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
+	<reg32 offset="0x9805" name="PC_UNKNOWN_9805" low="0" high="2"/>
 
 	<!-- probably a mirror of VFD_CONTROL_6 -->
-	<reg32 offset="0x9806" name="PC_PRIMID_CNTL">
-		<bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
-	</reg32>
+	<reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
+	<!-- 0x980b-0x983f invalid -->
 
+	<!-- 0x9840 - 0x9842 are not readable -->
 	<reg32 offset="0x9840" name="PC_DRAW_CMD">
 		<bitfield name="STATE_ID" low="0" high="7"/>
 	</reg32>
@@ -2816,19 +2806,21 @@ to upconvert to 32b float internally?
 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
 	</reg32>
 
-	<reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
+	<!-- 0x9843-0x997f invalid -->
 
 	<reg32 offset="0x9981" name="PC_POLYGON_MODE">
 		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
 	</reg32>
+	<reg32 offset="0x9980" name="PC_UNKNOWN_9980" low="0" high="2"/>
 
-	<reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
+	<!-- 0x9982-0x9aff invalid -->
 
 	<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
 		<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
 		<!-- maybe?  b1 seems always set, so just assume it is for now: -->
 		<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
 		<bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
+		<bitfield name="UNK3" pos="3" type="boolean"/>
 	</reg32>
 
 	<bitset name="a6xx_xs_out_cntl" inline="yes">
@@ -2839,52 +2831,70 @@ to upconvert to 32b float internally?
 		</doc>
 		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
 		<bitfield name="PSIZE" pos="8" type="boolean"/>
-		<!-- layer / primitiveid only for GS (apparently) -->
 		<bitfield name="LAYER" pos="9" type="boolean"/>
+		<bitfield name="VIEW" pos="10" type="boolean"/>
+		<!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
 		<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
 		<bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
 	</bitset>
 
 	<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
 	<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
-	<reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3"/>
+	<reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3" pos="11"/>
 	<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
 
 	<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
 		<doc>
 		  geometry shader
 		</doc>
+		<!-- TODO: first 16 bits are valid so something is wrong or missing here -->
 		<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
 		<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
 		<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
+		<bitfield name="UNK18" pos="18"/>
 	</reg32>
 
 	<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
 		<doc>
-		  size in vec4s of per-primitive storage for gs
+		  size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
 		</doc>
-		<bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
+		<bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
 	</reg32>
+	<!-- something gs related: -->
+	<reg32 offset="0x9b07" name="PC_UNKNOWN_9B07" low="0" high="6"/>
 
-	<reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
-
+	<reg32 offset="0x9b08" name="PC_UNKNOWN_9B08" low="0" high="15"/>
+	<!-- 0x9b09-0x9bff invalid -->
+	<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
+		<!-- special register (but note first 8 bits can be written/read) -->
+		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
+		<bitfield name="STATE_ID" low="8" high="15"/>
+	</reg32>
+	<!-- 0x9c01-0x9dff invalid -->
+	<!-- TODO: 0x9e00-0xa000 range incomplete -->
+	<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
+	<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL"/>
 	<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
 	<reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
+	<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
 
 	<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
 	<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
+		<bitfield name="UNK0" low="0" high="15"/>
 		<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
 		<bitfield name="VSC_N" low="22" high="26" type="uint"/>
 	</reg32>
-	<reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
-	<reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
-	<reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
-	<reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
-
-	<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
-		<bitfield name="STATE_ID" low="8" high="15"/>
-		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
-	</reg32>
+	<reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2" type="waddress" align="32"/>
+	<reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR" type="waddress" align="32"/>
+
+	<reg32 offset="0x9e34" name="PC_PERFCTR_PC_SEL_0"/>
+	<reg32 offset="0x9e35" name="PC_PERFCTR_PC_SEL_1"/>
+	<reg32 offset="0x9e36" name="PC_PERFCTR_PC_SEL_2"/>
+	<reg32 offset="0x9e37" name="PC_PERFCTR_PC_SEL_3"/>
+	<reg32 offset="0x9e38" name="PC_PERFCTR_PC_SEL_4"/>
+	<reg32 offset="0x9e39" name="PC_PERFCTR_PC_SEL_5"/>
+	<reg32 offset="0x9e3a" name="PC_PERFCTR_PC_SEL_6"/>
+	<reg32 offset="0x9e3b" name="PC_PERFCTR_PC_SEL_7"/>
 
 	<!-- always 0x0 -->
 	<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index c7c6df49a3f..e31f127f322 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -791,7 +791,6 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
 
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 249fd632a9a..b81482bd88c 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -893,8 +893,7 @@ tu6_emit_vpc(struct tu_cs *cs,
    tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
    tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
 
-   tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
-   tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+   tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
 
    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
    tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
@@ -2238,7 +2237,7 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
                    A6XX_VPC_POLYGON_MODE(mode));
 
    tu_cs_emit_regs(&cs,
-                   A6XX_PC_POLYGON_MODE(.mode = mode));
+                   A6XX_PC_POLYGON_MODE(mode));
 
    /* move to hw ctx init? */
    tu_cs_emit_regs(&cs,
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 2260f17b6a1..dd52edcc35a 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1190,7 +1190,6 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 
 	WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value);
 
-	WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
 	WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
 
 	WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 4ee227b027e..fb547560c44 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -831,8 +831,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
 	if (fs->instrlen)
 		fd6_emit_shader(ring, fs);
 
-	OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
-	OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+	OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
 
 	uint32_t non_sysval_input_count = 0;
 	for (uint32_t i = 0; i < vs->inputs_count; i++)
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
index 692e14ed48d..33c96377a0a 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
@@ -108,7 +108,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
 	}
 
 	OUT_REG(ring, A6XX_VPC_POLYGON_MODE(mode));
-	OUT_REG(ring, A6XX_PC_POLYGON_MODE(.mode = mode));
+	OUT_REG(ring, A6XX_PC_POLYGON_MODE(mode));
 
 	return ring;
 }