diff options
| author | Alyssa Rosenzweig <[email protected]> | 2020-05-11 13:49:03 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-21 17:49:14 +0000 |
| commit | cd26bd9425e80dc3236942913f6bf6d670943003 (patch) | |
| tree | ac743859f19460efb3a2479d7bb1800808c30f21 | |
| parent | 68d2a889b7a238b187cdf48afa2ed78874d3f23d (diff) | |
pan/mdg: Round up bytemasks when spilling
So we can pack the spills for <32-bit types.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
| -rw-r--r-- | src/panfrost/midgard/midgard_ra.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index e4901eed638..1ba193b7879 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -292,7 +292,8 @@ mir_lower_special_reads(compiler_context *ctx) } else { idx = spill_idx++; m = v_mov(i, idx); - m.mask = mir_from_bytemask(mir_bytemask_of_read_components(pre_use, i), 32); + m.mask = mir_from_bytemask(mir_round_bytemask_up( + mir_bytemask_of_read_components(pre_use, i), 32), 32); mir_insert_instruction_before(ctx, pre_use, m); mir_rewrite_index_src_single(pre_use, i, idx); } @@ -920,7 +921,8 @@ mir_spill_register( /* Mask the load based on the component count * actually needed to prevent RA loops */ - st.mask = mir_from_bytemask(read_bytemask, 32); + st.mask = mir_from_bytemask(mir_round_bytemask_up( + read_bytemask, 32), 32); mir_insert_instruction_before_scheduled(ctx, block, before, st); } else { |