diff options
| author | Marek Olšák <[email protected]> | 2016-10-05 01:49:30 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-10-05 21:03:54 +0200 |
| commit | cc4a19c4ad5b617af632ce732ccbfeb4b4043114 (patch) | |
| tree | 801450df48529f72eb6482f8c9e5e8907a712d1d | |
| parent | 844f8268e1cde496a854a72e080558f3c5700583 (diff) | |
radeonsi: fix texture border colors for compute shaders
There are VM faults without this.
Cc: 12.0 <[email protected]>
Acked-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_compute.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 9a5a4a9209f..1d1df2f6b70 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -208,6 +208,7 @@ static void si_set_global_binding( static void si_initialize_compute(struct si_context *sctx) { struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + uint64_t bc_va; radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); radeon_emit(cs, 0); @@ -242,6 +243,17 @@ static void si_initialize_compute(struct si_context *sctx) 0x190 /* Default value */); } + /* Set the pointer to border colors. */ + bc_va = sctx->border_color_buffer->gpu_address; + + if (sctx->b.chip_class >= CIK) { + radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2); + radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */ + radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */ + } else { + radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); + } + sctx->cs_shader_state.emitted_program = NULL; sctx->cs_shader_state.initialized = true; } |