intel/nir: Lower memory access bit sizes later

We're about to do load/store vectorization right before this but we need
that to happen after we've done a round of optimization.  Otherwise,
we'll be getting unoptimized NIR in from ANV and the vectorizer won't be
able to do anything with it.

Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>

1 files changed, 12 insertions, 2 deletions

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index c7e9c0e1129..8a6cc8fe696 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -861,8 +861,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    UNUSED bool progress; /* Written by OPT */
 
-   OPT(brw_nir_lower_mem_access_bit_sizes, devinfo);
-
    OPT(nir_opt_combine_memory_barriers, combine_all_barriers, NULL);
 
    do {
@@ -872,6 +870,18 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    brw_nir_optimize(nir, compiler, is_scalar, false);
 
+   if (OPT(brw_nir_lower_mem_access_bit_sizes, devinfo)) {
+      do {
+         progress = false;
+         OPT(nir_lower_pack);
+         OPT(nir_copy_prop);
+         OPT(nir_opt_dce);
+         OPT(nir_opt_cse);
+         OPT(nir_opt_algebraic);
+         OPT(nir_opt_constant_folding);
+      } while (progress);
+   }
+
    if (OPT(nir_lower_int64, nir->options->lower_int64_options))
       brw_nir_optimize(nir, compiler, is_scalar, false);