diff options
author | Jason Ekstrand <[email protected]> | 2020-01-27 14:42:20 -0600 |
---|---|---|
committer | Marge Bot <[email protected]> | 2020-01-28 18:15:29 +0000 |
commit | 997040e4b8353fe9b71a5e9fde2f933eae09c7a3 (patch) | |
tree | f88e838ea4722682904f128d71a9c15ff64c0ca2 | |
parent | 06657e1ddaa96f1e70aa499f244daff0ae1db571 (diff) |
intel/mi_builder: Force write completion on Gen12+
Otherwise, we have no guarantee that the write actually lands before we
move on to other things. Doing this on every SDI is probably a bit
harsh but it's safe. We should figure out a good way to avoid this when
we can.
Reviewed-by: Lionel Landwerlin <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
-rw-r--r-- | src/intel/common/gen_mi_builder.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/intel/common/gen_mi_builder.h b/src/intel/common/gen_mi_builder.h index dd7d87fc67a..bcd685754a3 100644 --- a/src/intel/common/gen_mi_builder.h +++ b/src/intel/common/gen_mi_builder.h @@ -358,6 +358,9 @@ _gen_mi_copy_no_unref(struct gen_mi_builder *b, case GEN_MI_VALUE_TYPE_IMM: gen_mi_builder_emit(b, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = dst.addr; +#if GEN_GEN >= 12 + sdi.ForceWriteCompletionCheck = true; +#endif sdi.ImmediateData = src.imm; } break; |