diff options
| author | Iago Toral Quiroga <[email protected]> | 2016-09-15 10:49:40 +0200 |
|---|---|---|
| committer | Samuel Iglesias Gonsálvez <[email protected]> | 2017-01-03 11:26:51 +0100 |
| commit | 8e92b402030735edab6c35e69dceee4acebb973b (patch) | |
| tree | 73878e17ccbd2e3860cd08e9f0e42b04609cb3f8 | |
| parent | 49d4d0268bc03fbf2a0688563c5d89a7c9eb1e8e (diff) | |
i965/vec4/tes: consider register offsets during attribute setup
Reviewed-by: Matt Turner <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_tes.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp index bb81ad3a155..ae6d99bed83 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp @@ -84,8 +84,8 @@ vec4_tes_visitor::setup_payload() bool is_64bit = type_sz(inst->src[i].type) == 8; - struct brw_reg grf = - brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2)); + unsigned slot = inst->src[i].nr + inst->src[i].offset / 16; + struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2)); grf = stride(grf, 0, is_64bit ? 2 : 4, 1); grf.swizzle = inst->src[i].swizzle; grf.type = inst->src[i].type; |