diff options
| author | Kenneth Graunke <[email protected]> | 2019-05-10 14:15:53 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2019-05-10 16:50:14 -0700 |
| commit | 72ccefb5298203c6e1c4b40b60b5dd356900ad47 (patch) | |
| tree | fda052745a3e5e80618c67db059d36df1c466e2c | |
| parent | 3610081daa47009aef23a7ab4471e7a71a073127 (diff) | |
iris: Use full ways for L3 cache setup on Icelake.
Anuj fixed this in i965 and anv, but the fix never landed in iris.
Fixes tessellation corruption on Icelake. Thanks to Rafael for
bisecting this and tracking it down.
Fixes: d0996d5fab6 iris: Emit default L3 config for the render pipeline
Reviewed-by: Rafael Antognolli <[email protected]>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 8c30b98aa49..2d02f631d00 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -631,6 +631,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg, * desirable behavior. */ reg.ErrorDetectionBehaviorControl = true; + reg.UseFullWays = true; #endif reg.URBAllocation = cfg->n[GEN_L3P_URB]; reg.ROAllocation = cfg->n[GEN_L3P_RO]; |