diff options
| author | Kenneth Graunke <[email protected]> | 2014-02-06 07:32:49 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-02-19 01:46:17 -0800 |
| commit | 577fdf1f4896041263b6de5980343c6721f6ec00 (patch) | |
| tree | 4888441d9dee7db1e03ddae2f6f9170f848be06e | |
| parent | a5d2eb6b98c87e58f158c0426dd180bc4aab53a0 (diff) | |
i965: Bump generation check in code to disable HiZ at LODs > 0.
Broadwell's "HiZ Resolve" operation still has the restriction that the
rectangle primitive must be 8x4 aligned. So I believe we still need
this.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 2198b8eab96..8e0d2beff86 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1237,7 +1237,7 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw, { assert(mt->hiz_mt); - if (brw->is_haswell) { + if (brw->gen >= 8 || brw->is_haswell) { uint32_t width = minify(mt->physical_width0, level); uint32_t height = minify(mt->physical_height0, level); |