diff options
| author | Alyssa Rosenzweig <[email protected]> | 2020-05-11 15:07:25 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-21 17:49:14 +0000 |
| commit | 553c2cf16b7612d4a70bd96230dad63777ec867e (patch) | |
| tree | d7d610eb4197b4c1469f507efbf75f9073ca4843 | |
| parent | b91d71597e4fba907d27f2a82f070c5a25abde5f (diff) | |
pan/mdg: Set RA bounds for fp16
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
| -rw-r--r-- | src/panfrost/midgard/midgard_ra.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index faaa41f2839..e4901eed638 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -525,13 +525,25 @@ allocate_registers(compiler_context *ctx, bool *spilled) (size == 64) ? 3 : /* (1 << 3) = 8-byte */ 3; /* 8-bit todo */ + /* We can't cross xy/zw boundaries. TODO: vec8 can */ + if (size == 16) + min_bound[dest] = 8; + /* We don't have a swizzle for the conditional and we don't * want to muck with the conditional itself, so just force * alignment for now */ - if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op)) + if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op)) { min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */ + /* LCRA assumes bound >= alignment */ + min_bound[dest] = 16; + } + + /* Since ld/st swizzles and masks are 32-bit only, we need them + * aligned to enable final packing */ + if (ins->type == TAG_LOAD_STORE_4) + min_alignment[dest] = MAX2(min_alignment[dest], 2); } for (unsigned i = 0; i < ctx->temp_count; ++i) { |