diff options
| author | Rhys Perry <[email protected]> | 2019-12-09 13:38:47 +0000 |
|---|---|---|
| committer | Rhys Perry <[email protected]> | 2020-01-13 13:25:32 +0000 |
| commit | 49bcd06f974dcd8f60b4aa7d93bf1843439126a2 (patch) | |
| tree | a1ab3116a7d16954468691f7ab1bff2c809c62ae | |
| parent | 632885741f74c12dedd4f128bba45e6a7f8d8982 (diff) | |
aco: set vm for pos0 exports on GFX10
RADV's LLVM backend and radeonsi does the same thing.
Signed-off-by: Rhys Perry <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Cc: 19.3 <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
| -rw-r--r-- | src/amd/compiler/aco_assembler.cpp | 2 | ||||
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 7 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index 207c40acf49..69b8a9b33c6 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -627,7 +627,7 @@ void fix_exports(asm_context& ctx, std::vector<uint32_t>& out, Program* program) exp->enabled_mask = 0; exp->compressed = false; exp->done = true; - exp->valid_mask = program->stage & hw_fs; + exp->valid_mask = (program->stage & hw_fs) || program->chip_class >= GFX10; if (program->stage & hw_fs) exp->dest = 9; /* NULL */ else diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index de2132c91db..d6b7dc696d5 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -7739,7 +7739,10 @@ static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *nex else exp->operands[i] = Operand(v1); } - exp->valid_mask = false; + /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang. + * Setting valid_mask=1 prevents it and has no other effect. + */ + exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0; exp->done = false; exp->compressed = false; if (is_pos) @@ -7779,7 +7782,7 @@ static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos) exp->enabled_mask |= 0x4; } } - exp->valid_mask = false; + exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0; exp->done = false; exp->compressed = false; exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++; |