diff options
| author | Matt Turner <[email protected]> | 2015-04-02 16:57:10 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2015-04-21 09:24:48 -0700 |
| commit | 3b4abdae041802183fa7d3792a21bf9ca10df96e (patch) | |
| tree | 464ac90c4b2a67f378f3693b547380c7478e5079 | |
| parent | 958b4965a23f69085dc04df165d6fccc2707d60e (diff) | |
i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.
The BSpec says this applies to Gen6 as well.
Reviewed-by: Jason Ekstrand <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index b06a947519c..a732a8984bf 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -428,7 +428,7 @@ fs_generator::generate_linterp(fs_inst *inst, if (brw->has_pln && delta_y.nr == delta_x.nr + 1 && - (brw->gen >= 6 || (delta_x.nr & 1) == 0)) { + (brw->gen >= 7 || (delta_x.nr & 1) == 0)) { brw_PLN(p, dst, interp, delta_x); } else { brw_LINE(p, brw_null_reg(), interp, delta_x); diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 2dfafdf9d6c..2a4054a29b7 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -245,9 +245,9 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) assert(reg == ra_reg_count); /* Add a special class for aligned pairs, which we'll put delta_x/y - * in on gen5 so that we can do PLN. + * in on Gen <= 6 so that we can do PLN. */ - if (devinfo->has_pln && reg_width == 1 && devinfo->gen < 6) { + if (devinfo->has_pln && reg_width == 1 && devinfo->gen <= 6) { aligned_pairs_class = ra_alloc_reg_class(regs); for (int i = 0; i < pairs_reg_count; i++) { |