vc4: Add support for texture tiling.

This still treats everything as RGBA8888 for the most part, same as
before.  This is a prerequisite for handling other texture formats, since
only RGBA8888 has a raster-layout mode.

10 files changed, 626 insertions, 53 deletions

diff --git a/src/gallium/drivers/vc4/Makefile.sources b/src/gallium/drivers/vc4/Makefile.sources
index 414a64ab472..68badc495b9 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -19,4 +19,5 @@ C_SOURCES := \
 	vc4_simulator_validate.c \
 	vc4_simulator_validate_shaders.c \
 	vc4_state.c \
+	vc4_tiling.c \
 	$()
diff --git a/src/gallium/drivers/vc4/vc4_context.c b/src/gallium/drivers/vc4/vc4_context.c
index 5d698a84798..0a09d399261 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -64,7 +64,7 @@ vc4_setup_rcl(struct vc4_context *vc4)
         cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset);
         cl_u16(&vc4->rcl, width);
         cl_u16(&vc4->rcl, height);
-        cl_u16(&vc4->rcl, ((ctex->tiling <<
+        cl_u16(&vc4->rcl, ((csurf->tiling <<
                             VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
                            VC4_RENDER_CONFIG_FORMAT_RGBA8888 |
                            VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE));
@@ -97,7 +97,7 @@ vc4_setup_rcl(struct vc4_context *vc4)
                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
                                 cl_u8(&vc4->rcl,
                                       VC4_LOADSTORE_TILE_BUFFER_COLOR |
-                                      (ctex->tiling <<
+                                      (csurf->tiling <<
                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
                                 cl_u8(&vc4->rcl,
                                       VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
@@ -295,7 +295,7 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv)
         vc4->dirty = ~0;
         vc4->fd = screen->fd;
 
-        util_slab_create(&vc4->transfer_pool, sizeof(struct pipe_transfer),
+        util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
                          16, UTIL_SLAB_SINGLETHREADED);
         vc4->blitter = util_blitter_create(pctx);
         if (!vc4->blitter)
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index fb1a2fe47bf..eed0ee1543b 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1438,7 +1438,8 @@ write_texture_p0(struct vc4_context *vc4,
         struct vc4_resource *rsc = vc4_resource(texture->texture);
 
         cl_reloc(vc4, &vc4->uniforms, rsc->bo,
-                 rsc->slices[0].offset | texture->u.tex.last_level);
+                 rsc->slices[0].offset | texture->u.tex.last_level |
+                 ((rsc->vc4_format & 7) << 4));
 }
 
 static void
@@ -1447,6 +1448,7 @@ write_texture_p1(struct vc4_context *vc4,
                  uint32_t unit)
 {
         struct pipe_sampler_view *texture = texstate->textures[unit];
+        struct vc4_resource *rsc = vc4_resource(texture->texture);
         struct pipe_sampler_state *sampler = texstate->samplers[unit];
         static const uint32_t mipfilter_map[] = {
                 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
@@ -1459,7 +1461,7 @@ write_texture_p1(struct vc4_context *vc4,
         };
 
         cl_u32(&vc4->uniforms,
-               (1 << 31) /* XXX: data type */|
+               ((rsc->vc4_format >> 4) << 31) |
                (texture->texture->height0 << 20) |
                (texture->texture->width0 << 8) |
                (imgfilter_map[sampler->mag_img_filter] << 7) |
diff --git a/src/gallium/drivers/vc4/vc4_resource.c b/src/gallium/drivers/vc4/vc4_resource.c
index c2978c0433a..fb46be3916b 100644
--- a/src/gallium/drivers/vc4/vc4_resource.c
+++ b/src/gallium/drivers/vc4/vc4_resource.c
@@ -31,12 +31,28 @@
 #include "vc4_screen.h"
 #include "vc4_context.h"
 #include "vc4_resource.h"
+#include "vc4_tiling.h"
 
 static void
 vc4_resource_transfer_unmap(struct pipe_context *pctx,
                             struct pipe_transfer *ptrans)
 {
         struct vc4_context *vc4 = vc4_context(pctx);
+        struct vc4_transfer *trans = vc4_transfer(ptrans);
+        struct pipe_resource *prsc = ptrans->resource;
+        struct vc4_resource *rsc = vc4_resource(prsc);
+        struct vc4_resource_slice *slice = &rsc->slices[ptrans->level];
+
+        if (trans->map) {
+                if (ptrans->usage & PIPE_TRANSFER_WRITE) {
+                        vc4_store_tiled_image(rsc->bo->map + slice->offset,
+                                              slice->stride,
+                                              trans->map, ptrans->stride,
+                                              slice->tiling, rsc->cpp,
+                                              &ptrans->box);
+                }
+                free(trans->map);
+        }
 
         pipe_resource_reference(&ptrans->resource, NULL);
         util_slab_free(&vc4->transfer_pool, ptrans);
@@ -51,25 +67,30 @@ vc4_resource_transfer_map(struct pipe_context *pctx,
 {
         struct vc4_context *vc4 = vc4_context(pctx);
         struct vc4_resource *rsc = vc4_resource(prsc);
+        struct vc4_resource_slice *slice = &rsc->slices[level];
+        struct vc4_transfer *trans;
         struct pipe_transfer *ptrans;
         enum pipe_format format = prsc->format;
         char *buf;
 
         vc4_flush_for_bo(pctx, rsc->bo);
 
-        ptrans = util_slab_alloc(&vc4->transfer_pool);
-        if (!ptrans)
+        trans = util_slab_alloc(&vc4->transfer_pool);
+        if (!trans)
                 return NULL;
 
+        /* XXX: Handle DISCARD_WHOLE_RESOURCE, DONTBLOCK, UNSYNCHRONIZED,
+         * DISCARD_WHOLE_RESOURCE, PERSISTENT, COHERENT.
+         */
+
         /* util_slab_alloc() doesn't zero: */
-        memset(ptrans, 0, sizeof(*ptrans));
+        memset(trans, 0, sizeof(*trans));
+        ptrans = &trans->base;
 
         pipe_resource_reference(&ptrans->resource, prsc);
         ptrans->level = level;
         ptrans->usage = usage;
         ptrans->box = *box;
-        ptrans->stride = rsc->slices[level].stride;
-        ptrans->layer_stride = ptrans->stride;
 
         /* Note that the current kernel implementation is synchronous, so no
          * need to do syncing stuff here yet.
@@ -83,10 +104,52 @@ vc4_resource_transfer_map(struct pipe_context *pctx,
 
         *pptrans = ptrans;
 
-        return buf + rsc->slices[level].offset +
-                box->y / util_format_get_blockheight(format) * ptrans->stride +
-                box->x / util_format_get_blockwidth(format) * rsc->cpp +
-                box->z * rsc->slices[level].size0;
+        if (rsc->tiled) {
+                uint32_t utile_w = vc4_utile_width(rsc->cpp);
+                uint32_t utile_h = vc4_utile_height(rsc->cpp);
+
+                /* No direct mappings of tiled, since we need to manually
+                 * tile/untile.
+                 */
+                if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
+                        return NULL;
+
+                /* We need to align the box to utile boundaries, since that's
+                 * what load/store operate on.
+                 */
+                uint32_t box_start_x = ptrans->box.x & (utile_w - 1);
+                uint32_t box_start_y = ptrans->box.y & (utile_h - 1);
+                ptrans->box.width += box_start_x;
+                ptrans->box.x -= box_start_x;
+                ptrans->box.height += box_start_y;
+                ptrans->box.y -= box_start_y;
+                ptrans->box.width = align(ptrans->box.width, utile_w);
+                ptrans->box.height = align(ptrans->box.height, utile_h);
+
+                ptrans->stride = ptrans->box.width * rsc->cpp;
+                ptrans->layer_stride = ptrans->stride;
+
+                trans->map = malloc(ptrans->stride * ptrans->box.height);
+                if (usage & PIPE_TRANSFER_READ) {
+                        vc4_load_tiled_image(trans->map, ptrans->stride,
+                                             buf + slice->offset,
+                                             slice->stride,
+                                             slice->tiling, rsc->cpp,
+                                             &ptrans->box);
+                }
+                return (trans->map +
+                        box_start_x * rsc->cpp +
+                        box_start_y * ptrans->stride);
+        } else {
+                ptrans->stride = slice->stride;
+                ptrans->layer_stride = ptrans->stride;
+
+                return buf + slice->offset +
+                        box->y / util_format_get_blockheight(format) * ptrans->stride +
+                        box->x / util_format_get_blockwidth(format) * rsc->cpp +
+                        box->z * slice->size0;
+        }
+
 
 fail:
         vc4_resource_transfer_unmap(pctx, ptrans);
@@ -130,14 +193,34 @@ vc4_setup_slices(struct vc4_resource *rsc)
         uint32_t height = prsc->height0;
         uint32_t depth = prsc->depth0;
         uint32_t offset = 0;
+        uint32_t utile_w = vc4_utile_width(rsc->cpp);
+        uint32_t utile_h = vc4_utile_height(rsc->cpp);
 
         for (int i = prsc->last_level; i >= 0; i--) {
                 struct vc4_resource_slice *slice = &rsc->slices[i];
                 uint32_t level_width = u_minify(width, i);
                 uint32_t level_height = u_minify(height, i);
 
+                if (rsc->tiled == VC4_TILING_FORMAT_LINEAR) {
+                        slice->tiling = VC4_TILING_FORMAT_LINEAR;
+                        level_width = align(level_width, 16);
+                } else {
+                        if (vc4_size_is_lt(level_width, level_height,
+                                           rsc->cpp)) {
+                                slice->tiling = VC4_TILING_FORMAT_LT;
+                                level_width = align(level_width, utile_w);
+                                level_height = align(level_height, utile_h);
+                        } else {
+                                slice->tiling = VC4_TILING_FORMAT_T;
+                                level_width = align(level_width,
+                                                    4 * 2 * utile_w);
+                                level_height = align(level_height,
+                                                     4 * 2 * utile_h);
+                        }
+                }
+
                 slice->offset = offset;
-                slice->stride = align(level_width * rsc->cpp, 16);
+                slice->stride = level_width * rsc->cpp;
                 slice->size0 = level_height * slice->stride;
 
                 /* Note, since we have cubes but no 3D, depth is invariant
@@ -180,6 +263,17 @@ vc4_resource_setup(struct pipe_screen *pscreen,
         return rsc;
 }
 
+static enum vc4_texture_data_type
+get_resource_texture_format(struct pipe_resource *prsc)
+{
+        struct vc4_resource *rsc = vc4_resource(prsc);
+
+        if (rsc->tiled)
+                return VC4_TEXTURE_TYPE_RGBA8888;
+        else
+                return VC4_TEXTURE_TYPE_RGBA32R;
+}
+
 static struct pipe_resource *
 vc4_resource_create(struct pipe_screen *pscreen,
                     const struct pipe_resource *tmpl)
@@ -187,9 +281,21 @@ vc4_resource_create(struct pipe_screen *pscreen,
         struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
         struct pipe_resource *prsc = &rsc->base.b;
 
+        /* We have to make shared be untiled, since we don't have any way to
+         * communicate metadata about tiling currently.
+         */
+        if (tmpl->target == PIPE_BUFFER ||
+            (tmpl->bind & (PIPE_BIND_SCANOUT |
+                           PIPE_BIND_LINEAR |
+                           PIPE_BIND_SHARED |
+                           PIPE_BIND_CURSOR))) {
+                rsc->tiled = false;
+        } else {
+                rsc->tiled = true;
+        }
+
         vc4_setup_slices(rsc);
 
-        rsc->tiling = VC4_TILING_FORMAT_LINEAR;
         rsc->bo = vc4_bo_alloc(vc4_screen(pscreen),
                                rsc->slices[0].offset +
                                rsc->slices[0].size0 * prsc->depth0,
@@ -197,6 +303,9 @@ vc4_resource_create(struct pipe_screen *pscreen,
         if (!rsc->bo)
                 goto fail;
 
+        if (tmpl->target != PIPE_BUFFER)
+                rsc->vc4_format = get_resource_texture_format(prsc);
+
         return prsc;
 fail:
         vc4_resource_destroy(pscreen, prsc);
@@ -215,7 +324,7 @@ vc4_resource_from_handle(struct pipe_screen *pscreen,
         if (!rsc)
                 return NULL;
 
-        rsc->tiling = VC4_TILING_FORMAT_LINEAR;
+        rsc->tiled = false;
         rsc->bo = vc4_screen_bo_from_handle(pscreen, handle, &slice->stride);
         if (!rsc->bo)
                 goto fail;
@@ -223,6 +332,9 @@ vc4_resource_from_handle(struct pipe_screen *pscreen,
 #ifdef USE_VC4_SIMULATOR
         slice->stride = align(prsc->width0 * rsc->cpp, 16);
 #endif
+        slice->tiling = VC4_TILING_FORMAT_LINEAR;
+
+        rsc->vc4_format = get_resource_texture_format(prsc);
 
         return prsc;
 
@@ -258,6 +370,7 @@ vc4_create_surface(struct pipe_context *pctx,
         psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
         psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
         surface->offset = rsc->slices[level].offset;
+        surface->tiling = rsc->slices[level].tiling;
 
         return &surface->base;
 }
diff --git a/src/gallium/drivers/vc4/vc4_resource.h b/src/gallium/drivers/vc4/vc4_resource.h
index 34ca7ec8abb..caefbd057c0 100644
--- a/src/gallium/drivers/vc4/vc4_resource.h
+++ b/src/gallium/drivers/vc4/vc4_resource.h
@@ -26,12 +26,20 @@
 #define VC4_RESOURCE_H
 
 #include "vc4_screen.h"
+#include "vc4_packet.h"
 #include "util/u_transfer.h"
 
+struct vc4_transfer {
+        struct pipe_transfer base;
+        void *map;
+};
+
 struct vc4_resource_slice {
         uint32_t offset;
         uint32_t stride;
         uint32_t size0;
+        /** One of VC4_TILING_FORMAT_* */
+        uint8_t tiling;
 };
 
 struct vc4_surface {
@@ -41,6 +49,7 @@ struct vc4_surface {
         uint32_t width;
         uint16_t height;
         uint16_t depth;
+        uint8_t tiling;
 };
 
 struct vc4_resource {
@@ -48,8 +57,9 @@ struct vc4_resource {
         struct vc4_bo *bo;
         struct vc4_resource_slice slices[VC4_MAX_MIP_LEVELS];
         int cpp;
-        /** One of VC4_TILING_FORMAT_* */
-        uint8_t tiling;
+        bool tiled;
+        /** One of VC4_TEXTURE_TYPE_* */
+        enum vc4_texture_data_type vc4_format;
 };
 
 static INLINE struct vc4_resource *
@@ -64,6 +74,12 @@ vc4_surface(struct pipe_surface *psurf)
         return (struct vc4_surface *)psurf;
 }
 
+static INLINE struct vc4_transfer *
+vc4_transfer(struct pipe_transfer *ptrans)
+{
+        return (struct vc4_transfer *)ptrans;
+}
+
 void vc4_resource_screen_init(struct pipe_screen *pscreen);
 void vc4_resource_context_init(struct pipe_context *pctx);
 
diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c
index feff50c4b05..0c62b446b4e 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -302,7 +302,7 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
         return 0;
 }
 
-uint8_t
+static uint8_t
 vc4_get_texture_format(enum pipe_format format)
 {
         switch (format) {
diff --git a/src/gallium/drivers/vc4/vc4_screen.h b/src/gallium/drivers/vc4/vc4_screen.h
index 5cfdcaeed9f..a45a6e7a365 100644
--- a/src/gallium/drivers/vc4/vc4_screen.h
+++ b/src/gallium/drivers/vc4/vc4_screen.h
@@ -64,8 +64,6 @@ vc4_screen_bo_from_handle(struct pipe_screen *pscreen,
                           struct winsys_handle *whandle,
                           unsigned *out_stride);
 
-uint8_t vc4_get_texture_format(enum pipe_format format);
-
 extern uint32_t vc4_debug;
 
 #endif /* VC4_SCREEN_H */
diff --git a/src/gallium/drivers/vc4/vc4_simulator_validate.c b/src/gallium/drivers/vc4/vc4_simulator_validate.c
index c062d8a25bd..00ec301dbb6 100644
--- a/src/gallium/drivers/vc4/vc4_simulator_validate.c
+++ b/src/gallium/drivers/vc4/vc4_simulator_validate.c
@@ -47,6 +47,53 @@
 	void *validated,				\
 	void *untrusted
 
+
+/** Return the width in pixels of a 64-byte microtile. */
+static uint32_t
+utile_width(int cpp)
+{
+	switch (cpp) {
+	case 1:
+	case 2:
+		return 8;
+	case 4:
+		return 4;
+	case 8:
+		return 2;
+	default:
+		DRM_ERROR("unknown cpp: %d\n", cpp);
+		return 1;
+	}
+}
+
+/** Return the height in pixels of a 64-byte microtile. */
+static uint32_t
+utile_height(int cpp)
+{
+	switch (cpp) {
+	case 1:
+		return 8;
+	case 2:
+	case 4:
+	case 8:
+		return 4;
+	default:
+		DRM_ERROR("unknown cpp: %d\n", cpp);
+		return 1;
+	}
+}
+
+/**
+ * The texture unit decides what tiling format a particular miplevel is using
+ * this function, so we lay out our miptrees accordingly.
+ */
+static bool
+size_is_lt(uint32_t width, uint32_t height, int cpp)
+{
+	return (width <= 4 * utile_width(cpp) ||
+		height <= 4 * utile_height(cpp));
+}
+
 static bool
 vc4_use_bo(struct exec_info *exec,
 	   uint32_t hindex,
@@ -105,47 +152,50 @@ check_tex_size(struct exec_info *exec, struct drm_gem_cma_object *fbo,
 	       uint32_t offset, uint8_t tiling_format,
 	       uint32_t width, uint32_t height, uint8_t cpp)
 {
-	uint32_t width_align, height_align;
-	uint32_t aligned_row_len, aligned_h, size;
+	uint32_t aligned_width, aligned_height, stride, size;
+	uint32_t utile_w = utile_width(cpp);
+	uint32_t utile_h = utile_height(cpp);
+
+	/* The values are limited by the packet/texture parameter bitfields,
+	 * so we don't need to worry as much about integer overflow.
+	 */
+	BUG_ON(width > 65535);
+	BUG_ON(height > 65535);
 
 	switch (tiling_format) {
 	case VC4_TILING_FORMAT_LINEAR:
-		width_align = 16;
-		height_align = 1;
+		aligned_width = roundup(width, 16 / cpp);
+		aligned_height = height;
 		break;
 	case VC4_TILING_FORMAT_T:
-		width_align = 128;
-		height_align = 32;
+		aligned_width = roundup(width, utile_w * 8);
+		aligned_height = roundup(height, utile_h * 8);
 		break;
 	case VC4_TILING_FORMAT_LT:
-		width_align = 16;
-		height_align = 4;
+		aligned_width = roundup(width, utile_w);
+		aligned_height = roundup(height, utile_h);
 		break;
 	default:
 		DRM_ERROR("buffer tiling %d unsupported\n", tiling_format);
 		return false;
 	}
 
-	/* The values are limited by the packet/texture parameter bitfields,
-	 * so we don't need to worry as much about integer overflow.
-	 */
-	BUG_ON(width > 65535);
-	BUG_ON(height > 65535);
-
-	aligned_row_len = roundup(width * cpp, width_align);
-	aligned_h = roundup(height, height_align);
+	stride = aligned_width * cpp;
 
-	if (INT_MAX / aligned_row_len < aligned_h) {
-		DRM_ERROR("Overflow in fbo size (%d * %d)\n",
-			  aligned_row_len, aligned_h);
+	if (INT_MAX / stride < aligned_height) {
+		DRM_ERROR("Overflow in fbo size (%dx%d -> %dx%d)\n",
+			  width, height,
+			  aligned_width, aligned_height);
 		return false;
 	}
-	size = aligned_row_len * aligned_h;
+	size = stride * aligned_height;
 
 	if (size + offset < size ||
 	    size + offset > fbo->base.size) {
-		DRM_ERROR("Overflow in %dx%d fbo size (%d + %d > %d)\n",
-			  width, height, size, offset, fbo->base.size);
+		DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n",
+			  width, height,
+			  aligned_width, aligned_height,
+			  size, offset, fbo->base.size);
 		return false;
 	}
 
@@ -706,8 +756,8 @@ reloc_tex(struct exec_info *exec,
 	uint32_t miplevels = (p0 & 15);
 	uint32_t width = (p1 >> 8) & 2047;
 	uint32_t height = (p1 >> 20) & 2047;
-	uint32_t cpp, tiling_format;
-	int i;
+	uint32_t cpp, tiling_format, utile_w, utile_h;
+	uint32_t i;
 	enum vc4_texture_data_type type;
 
 	if (width == 0)
@@ -751,12 +801,16 @@ reloc_tex(struct exec_info *exec,
 		DRM_ERROR("Texture format %d unsupported\n", type);
 		return false;
 	}
+	utile_w = utile_width(cpp);
+	utile_h = utile_height(cpp);
 
 	if (type == VC4_TEXTURE_TYPE_RGBA32R) {
 		tiling_format = VC4_TILING_FORMAT_LINEAR;
 	} else {
-		DRM_ERROR("Tiling formats not yet supported\n");
-		return false;
+		if (size_is_lt(width, height, cpp))
+			tiling_format = VC4_TILING_FORMAT_LT;
+		else
+			tiling_format = VC4_TILING_FORMAT_T;
 	}
 
 	if (!vc4_use_bo(exec, texture_handle_index, VC4_MODE_RENDER, &tex))
@@ -771,17 +825,44 @@ reloc_tex(struct exec_info *exec,
 	 * sure there is actually space in the BO.
 	 */
 	for (i = 1; i <= miplevels; i++) {
-		uint32_t level_width = align(max(width >> i, 1), 16 / cpp);
-		uint32_t level_height = max(height >> i, 1);
-		uint32_t level_size = level_width * level_height * cpp;
+		uint32_t level_width = max(width >> i, 1u);
+		uint32_t level_height = max(height >> i, 1u);
+		uint32_t aligned_width, aligned_height;
+		uint32_t level_size;
+
+		/* Once the levels get small enough, they drop from T to LT. */
+		if (tiling_format == VC4_TILING_FORMAT_T &&
+		    size_is_lt(level_width, level_height, cpp)) {
+			tiling_format = VC4_TILING_FORMAT_LT;
+		}
+
+		switch (tiling_format) {
+		case VC4_TILING_FORMAT_T:
+			aligned_width = roundup(level_width, utile_w * 8);
+			aligned_height = roundup(level_height, utile_h * 8);
+			break;
+		case VC4_TILING_FORMAT_LT:
+			aligned_width = roundup(level_width, utile_w);
+			aligned_height = roundup(level_height, utile_h);
+			break;
+		default:
+			aligned_width = roundup(level_width, 16 / cpp);
+			aligned_height = height;
+			break;
+		}
+
+		level_size = aligned_width * cpp * aligned_height;
 
 		if (offset < level_size) {
-			DRM_ERROR("Level %d (%dx%d) size %db overflowed "
-				  "buffer bounds (offset %d)\n",
+			DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db "
+				  "overflowed buffer bounds (offset %d)\n",
 				  i, level_width, level_height,
+				  aligned_width, aligned_height,
 				  level_size, offset);
 			return false;
 		}
+
+		offset -= level_size;
 	}
 
 	*validated_p0 = tex->paddr + p0;
diff --git a/src/gallium/drivers/vc4/vc4_tiling.c b/src/gallium/drivers/vc4/vc4_tiling.c
new file mode 100644
index 00000000000..f9801c9cefd
--- /dev/null
+++ b/src/gallium/drivers/vc4/vc4_tiling.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright © 2014 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/** @file vc4_tiling.c
+ *
+ * Handles information about the VC4 tiling formats, and loading and storing
+ * from them.
+ *
+ * Texture mipmap levels on VC4 are (with the exception of 32-bit RGBA raster
+ * textures for scanout) stored as groups of microtiles.  If the texture is at
+ * least 4x4 microtiles (utiles), then those microtiles are arranged in a sort
+ * of Hilbert-fractal-ish layout (T), otherwise the microtiles are in raster
+ * order (LT).
+ *
+ * Specifically, the T format has:
+ *
+ * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
+ *   pixels at 32 bit depth.
+ *
+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
+ *   16x16 pixels).
+ *
+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
+ *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
+ *   they're (TR, BR, BL, TL), where bottom left is start of memory.
+ *
+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
+ *   tiles) or right-to-left (odd rows of 4k tiles).
+ */
+
+#include "vc4_screen.h"
+#include "vc4_context.h"
+#include "vc4_tiling.h"
+
+/** Return the width in pixels of a 64-byte microtile. */
+uint32_t
+vc4_utile_width(int cpp)
+{
+        switch (cpp) {
+        case 1:
+        case 2:
+                return 8;
+        case 4:
+                return 4;
+        case 8:
+                return 2;
+        default:
+                fprintf(stderr, "unknown cpp: %d\n", cpp);
+                abort();
+        }
+}
+
+/** Return the height in pixels of a 64-byte microtile. */
+uint32_t
+vc4_utile_height(int cpp)
+{
+        switch (cpp) {
+        case 1:
+                return 8;
+        case 2:
+        case 4:
+        case 8:
+                return 4;
+        default:
+                fprintf(stderr, "unknown cpp: %d\n", cpp);
+                abort();
+        }
+}
+
+/**
+ * The texture unit decides what tiling format a particular miplevel is using
+ * this function, so we lay out our miptrees accordingly.
+ */
+bool
+vc4_size_is_lt(uint32_t width, uint32_t height, int cpp)
+{
+        return (width <= 4 * vc4_utile_width(cpp) ||
+                height <= 4 * vc4_utile_height(cpp));
+}
+
+void
+vc4_load_utile(void *dst, void *src, uint32_t dst_stride, uint32_t cpp)
+{
+        uint32_t utile_h = vc4_utile_height(cpp);
+        uint32_t row_size = 64 / utile_h;
+
+        for (int y = 0; y < utile_h; y++) {
+                memcpy(dst, src, row_size);
+                dst += dst_stride;
+                src += row_size;
+        }
+}
+
+void
+vc4_store_utile(void *dst, void *src, uint32_t src_stride, uint32_t cpp)
+{
+        uint32_t utile_h = vc4_utile_height(cpp);
+        uint32_t row_size = 64 / utile_h;
+
+        for (int y = 0; y < utile_h; y++) {
+                memcpy(dst, src, row_size);
+                dst += row_size;
+                src += src_stride;
+        }
+}
+
+static void
+check_box_utile_alignment(const struct pipe_box *box, int cpp)
+{
+        uint32_t utile_w = vc4_utile_width(cpp);
+        uint32_t utile_h = vc4_utile_height(cpp);
+
+        assert(!(box->x & (utile_w - 1)));
+        assert(!(box->y & (utile_h - 1)));
+        assert(!(box->width & (utile_w - 1)));
+        assert(!(box->height & (utile_h - 1)));
+}
+
+static void
+vc4_load_lt_image(void *dst, uint32_t dst_stride,
+                  void *src, uint32_t src_stride,
+                  int cpp, const struct pipe_box *box)
+{
+        uint32_t utile_w = vc4_utile_width(cpp);
+        uint32_t utile_h = vc4_utile_height(cpp);
+        uint32_t xstart = box->x / utile_w;
+        uint32_t ystart = box->y / utile_h;
+
+        for (uint32_t y = 0; y < box->height; y += utile_h) {
+                for (int x = 0; x < box->width; x += utile_w) {
+                        vc4_load_utile(dst + (dst_stride * y +
+                                              x * cpp),
+                                       src + ((ystart + y) * src_stride +
+                                              (xstart + x) * 64 / utile_w),
+                                       dst_stride, cpp);
+                }
+        }
+}
+
+static void
+vc4_store_lt_image(void *dst, uint32_t dst_stride,
+                   void *src, uint32_t src_stride,
+                   int cpp, const struct pipe_box *box)
+{
+        uint32_t utile_w = vc4_utile_width(cpp);
+        uint32_t utile_h = vc4_utile_height(cpp);
+        uint32_t xstart = box->x / utile_w;
+        uint32_t ystart = box->y / utile_h;
+
+        for (uint32_t y = 0; y < box->height; y += utile_h) {
+                for (int x = 0; x < box->width; x += utile_w) {
+                        vc4_store_utile(dst + ((ystart + y) * dst_stride +
+                                               (xstart + x) * 64 / utile_w),
+                                        src + (src_stride * y +
+                                               x * cpp),
+                                        src_stride, cpp);
+                }
+        }
+}
+
+/**
+ * Takes a utile x and y (and the number of utiles of width of the image) and
+ * returns the offset to the utile within a VC4_TILING_FORMAT_TF image.
+ */
+static uint32_t
+t_utile_address(uint32_t utile_x, uint32_t utile_y,
+                uint32_t utile_stride)
+{
+        /* T images have to be aligned to 8 utiles (4x4 subtiles, which are
+         * 2x2 in a 4k tile).
+         */
+        assert(!(utile_stride & 7));
+        uint32_t tile_stride = utile_stride >> 3;
+        /* 4k tile offsets. */
+        uint32_t tile_x = utile_x >> 3;
+        uint32_t tile_y = utile_y >> 3;
+        bool odd_tile_y = tile_y & 1;
+
+        /* Odd lines of 4k tiles go right-to-left. */
+        if (odd_tile_y)
+                tile_x = tile_stride - tile_x - 1;
+
+        uint32_t tile_offset = 4096 * (tile_y * tile_stride + tile_x);
+
+        uint32_t stile_x = (utile_x >> 2) & 1;
+        uint32_t stile_y = (utile_y >> 2) & 1;
+        uint32_t stile_index = (stile_y << 1) + stile_x;
+        static const uint32_t odd_stile_map[4] = {2, 1, 3, 0};
+        static const uint32_t even_stile_map[4] = {0, 3, 1, 2};
+
+        uint32_t stile_offset = 1024 * (odd_tile_y ?
+                                        odd_stile_map[stile_index] :
+                                        even_stile_map[stile_index]);
+
+        uint32_t utile_offset = 64 * ((utile_y & 3) * 4 + (utile_x & 3));
+
+#if 0
+        fprintf(stderr, "utile %d,%d -> %d + %d + %d (stride %d,%d) = %d\n",
+                utile_x, utile_y,
+                tile_offset, stile_offset, utile_offset,
+                utile_stride, tile_stride,
+                tile_offset + stile_offset + utile_offset);
+#endif
+
+        return tile_offset + stile_offset + utile_offset;
+}
+
+static void
+vc4_load_t_image(void *dst, uint32_t dst_stride,
+                 void *src, uint32_t src_stride,
+                 int cpp, const struct pipe_box *box)
+{
+        uint32_t utile_w = vc4_utile_width(cpp);
+        uint32_t utile_h = vc4_utile_height(cpp);
+        uint32_t utile_stride = src_stride / cpp / utile_w;
+        uint32_t xstart = box->x / utile_w;
+        uint32_t ystart = box->y / utile_h;
+
+        for (uint32_t y = 0; y < box->height / utile_h; y++) {
+                for (int x = 0; x < box->width / utile_w; x++) {
+                        vc4_load_utile(dst + (y * utile_h * dst_stride +
+                                              x * utile_w * cpp),
+                                       src + t_utile_address(xstart + x,
+                                                             ystart + y,
+                                                             utile_stride),
+                                       dst_stride, cpp);
+                }
+        }
+}
+
+static void
+vc4_store_t_image(void *dst, uint32_t dst_stride,
+                  void *src, uint32_t src_stride,
+                  int cpp, const struct pipe_box *box)
+{
+        uint32_t utile_w = vc4_utile_width(cpp);
+        uint32_t utile_h = vc4_utile_height(cpp);
+        uint32_t utile_stride = dst_stride / cpp / utile_w;
+        uint32_t xstart = box->x / utile_w;
+        uint32_t ystart = box->y / utile_h;
+
+        for (uint32_t y = 0; y < box->height / utile_h; y++) {
+                for (int x = 0; x < box->width / utile_w; x++) {
+                        vc4_store_utile(dst + t_utile_address(xstart + x,
+                                                              ystart + y,
+                                                              utile_stride),
+                                        src + (y * utile_h * src_stride +
+                                               x * utile_w * cpp),
+                                        src_stride, cpp);
+                }
+        }
+}
+
+/**
+ * Loads pixel data from the start (microtile-aligned) box in @src to the
+ * start of @dst according to the given tiling format.
+ */
+void
+vc4_load_tiled_image(void *dst, uint32_t dst_stride,
+                     void *src, uint32_t src_stride,
+                     uint8_t tiling_format, int cpp,
+                     const struct pipe_box *box)
+{
+        check_box_utile_alignment(box, cpp);
+
+        if (tiling_format == VC4_TILING_FORMAT_LT) {
+                vc4_load_lt_image(dst, dst_stride,
+                                  src, src_stride,
+                                  cpp, box);
+        } else {
+                assert(tiling_format == VC4_TILING_FORMAT_T);
+                vc4_load_t_image(dst, dst_stride,
+                                 src, src_stride,
+                                 cpp, box);
+        }
+}
+
+/**
+ * Stores pixel data from the start of @src into a (microtile-aligned) box in
+ * @dst according to the given tiling format.
+ */
+void
+vc4_store_tiled_image(void *dst, uint32_t dst_stride,
+                      void *src, uint32_t src_stride,
+                      uint8_t tiling_format, int cpp,
+                      const struct pipe_box *box)
+{
+        check_box_utile_alignment(box, cpp);
+
+        if (tiling_format == VC4_TILING_FORMAT_LT) {
+                vc4_store_lt_image(dst, dst_stride,
+                                   src, src_stride,
+                                   cpp, box);
+        } else {
+                assert(tiling_format == VC4_TILING_FORMAT_T);
+                vc4_store_t_image(dst, dst_stride,
+                                  src, src_stride,
+                                  cpp, box);
+        }
+}
+
diff --git a/src/gallium/drivers/vc4/vc4_tiling.h b/src/gallium/drivers/vc4/vc4_tiling.h
new file mode 100644
index 00000000000..b5d10da3417
--- /dev/null
+++ b/src/gallium/drivers/vc4/vc4_tiling.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2014 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef VC4_TILING_H
+#define VC4_TILING_H
+
+uint32_t vc4_utile_width(int cpp);
+uint32_t vc4_utile_height(int cpp);
+bool vc4_size_is_lt(uint32_t width, uint32_t height, int cpp);
+void vc4_load_utile(void *dst, void *src, uint32_t dst_stride, uint32_t cpp);
+void vc4_store_utile(void *dst, void *src, uint32_t src_stride, uint32_t cpp);
+void vc4_load_tiled_image(void *dst, uint32_t dst_stride,
+                          void *src, uint32_t src_stride,
+                          uint8_t tiling_format, int cpp,
+                          const struct pipe_box *box);
+void vc4_store_tiled_image(void *dst, uint32_t dst_stride,
+                           void *src, uint32_t src_stride,
+                           uint8_t tiling_format, int cpp,
+                           const struct pipe_box *box);
+
+#endif /* VC4_TILING_H */