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authorIlia Mirkin <[email protected]>2016-09-02 23:57:06 -0400
committerIlia Mirkin <[email protected]>2016-09-03 00:01:07 -0400
commit163a029eba9aa73e3c0b624a3067218a01a3e47b (patch)
treea542033d2284c0bb443e22dee30189e2ede6ee26
parentd0cf7a6beb4470d945bccb4e753cc7eb6ca5dda8 (diff)
nv50,nvc0: respect render condition enable flag when clearing rt/zs
This is a newly added flag. We always pass false into it from nv50_clear_texture, but other callers may want to respect the render condition. (And the functions were originally spec'd to respect it.) Signed-off-by: Ilia Mirkin <[email protected]>
-rw-r--r--src/gallium/drivers/nouveau/nv50/nv50_surface.c24
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_surface.c12
2 files changed, 24 insertions, 12 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index 52e890786bd..a6c0bbc2671 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -342,8 +342,10 @@ nv50_clear_render_target(struct pipe_context *pipe,
PUSH_DATA (push, (width << 16) | dstx);
PUSH_DATA (push, (height << 16) | dsty);
- BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
- PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
+ if (!render_condition_enabled) {
+ BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
+ PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
+ }
BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
for (z = 0; z < sf->depth; ++z) {
@@ -351,8 +353,10 @@ nv50_clear_render_target(struct pipe_context *pipe,
(z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
}
- BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
- PUSH_DATA (push, nv50->cond_condmode);
+ if (!render_condition_enabled) {
+ BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
+ PUSH_DATA (push, nv50->cond_condmode);
+ }
nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
}
@@ -426,8 +430,10 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
PUSH_DATA (push, (width << 16) | dstx);
PUSH_DATA (push, (height << 16) | dsty);
- BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
- PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
+ if (!render_condition_enabled) {
+ BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
+ PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
+ }
BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
for (z = 0; z < sf->depth; ++z) {
@@ -435,8 +441,10 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
(z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
}
- BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
- PUSH_DATA (push, nv50->cond_condmode);
+ if (!render_condition_enabled) {
+ BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
+ PUSH_DATA (push, nv50->cond_condmode);
+ }
nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index a6ca6fb75a0..e3532421a84 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -344,7 +344,8 @@ nvc0_clear_render_target(struct pipe_context *pipe,
nvc0_resource_fence(res, NOUVEAU_BO_WR);
}
- IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
+ if (!render_condition_enabled)
+ IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
for (z = 0; z < sf->depth; ++z) {
@@ -352,7 +353,8 @@ nvc0_clear_render_target(struct pipe_context *pipe,
(z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
}
- IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
+ if (!render_condition_enabled)
+ IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
}
@@ -670,7 +672,8 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe,
PUSH_DATA (push, dst->u.tex.first_layer);
IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
- IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
+ if (!render_condition_enabled)
+ IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
for (z = 0; z < sf->depth; ++z) {
@@ -678,7 +681,8 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe,
(z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
}
- IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
+ if (!render_condition_enabled)
+ IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
}