diff options
| author | Francisco Jerez <[email protected]> | 2019-11-24 16:12:12 -0800 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2020-01-10 11:00:24 -0800 |
| commit | 0a6e46d44d30fd10ee6784c9a6920b4d127e9810 (patch) | |
| tree | 953add4212a0b091b4771e6b90a557cfae409206 | |
| parent | a30bb25a7a495db7b7cb3be50431029f48019fc3 (diff) | |
intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().
Prevents invalid code from being emitted for ROR/ROL instructions in
SIMD32 shaders.
The problem can be reproduced with the following tests while forcing
SIMD32 to be used for fragment shaders:
piglit.shaders.glsl-rotate-left
piglit.shaders.glsl-rotate-right
However the issue could occur in production already with compute
shaders and a workgroup size large enough to trigger SIMD32 dispatch.
Fixes: 83fdec0f0de "intel/compiler: Enable the emission of ROR/ROL instructions"
Cc: Sagar Ghuge <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index beeac84e43d..f78c953f0f3 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -6237,6 +6237,8 @@ get_lowered_simd_width(const struct gen_device_info *devinfo, case BRW_OPCODE_SHR: case BRW_OPCODE_SHL: case BRW_OPCODE_ASR: + case BRW_OPCODE_ROR: + case BRW_OPCODE_ROL: case BRW_OPCODE_CMPN: case BRW_OPCODE_CSEL: case BRW_OPCODE_F32TO16: |