aboutsummaryrefslogtreecommitdiffstats
path: root/src/utils/cpuid.h
blob: 0b210768a71dc9ceb2ba1c5a4ad6e5a685a24f6a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
/**
* Runtime CPU detection
* (C) 2009 Jack Lloyd
*
* Distributed under the terms of the Botan license
*/

#ifndef BOTAN_CPUID_H__
#define BOTAN_CPUID_H__

#include <botan/types.h>

namespace Botan {

class CPUID
   {
   public:
      enum CPUID_bits {
         CPUID_RDTSC_BIT = 4,
         CPUID_SSE2_BIT = 26,
         CPUID_SSSE3_BIT = 41,
         CPUID_SSE41_BIT = 51,
         CPUID_SSE42_BIT = 52,
         CPUID_INTEL_AES_BIT = 57,
      };

      /**
      * Return a best guess of the cache line size
      */
      static u32bit cache_line_size();

      /**
      * Check if the processor supports RDTSC
      */
      static bool has_rdtsc()
         { return ((x86_processor_flags() >> CPUID_RDTSC_BIT) & 1); }

      /**
      * Check if the processor supports SSE2
      */
      static bool has_sse2()
         { return ((x86_processor_flags() >> CPUID_SSE2_BIT) & 1); }

      /**
      * Check if the processor supports SSSE3
      */
      static bool has_ssse3()
         { return ((x86_processor_flags() >> CPUID_SSSE3_BIT) & 1); }

      /**
      * Check if the processor supports SSE4.1
      */
      static bool has_sse41()
         { return ((x86_processor_flags() >> CPUID_SSE41_BIT) & 1); }

      /**
      * Check if the processor supports SSE4.2
      */
      static bool has_sse42()
         { return ((x86_processor_flags() >> CPUID_SSE42_BIT) & 1); }

      /**
      * Check if the processor supports Intel AES instructions
      */
      static bool has_intel_aes()
         { return ((x86_processor_flags() >> CPUID_INTEL_AES_BIT) & 1); }

   private:
      static u64bit x86_processor_flags();
   };

}

#endif