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* Shuffle things around. Add NIST X.509 test to build.lloyd2014-01-011-153/+0
* Add CPUID::printlloyd2013-12-311-0/+3
* Clean up GCM. Add CLMUL support.lloyd2013-12-271-4/+4
* Add CPUID check for AVX-512lloyd2013-12-251-0/+7
* Add cpuid support for new x86 feature flags like AVX2 and RDSEEDlloyd2013-12-141-12/+41
* Always include modules requiring ISA extensions as long as thelloyd2013-04-171-7/+0
* We were checking the wrong bit for rdrand support. Found using SDE'slloyd2012-05-101-1/+1
* Detect (though not using) the CPUID bit for the RDRAND instructionlloyd2011-06-161-1/+8
* s/u32bit/size_t/ in utilslloyd2010-10-131-2/+2
* Add support in CPUID for detecting PCMULUDQ and MOVBE instructions.lloyd2010-07-271-4/+18
* Modify CPUID so all the check functions are purely inline. Add a newlloyd2010-07-261-9/+16
* Simplify feature checkslloyd2010-06-281-7/+12
* Add detection support for upcoming AVXlloyd2010-06-251-1/+8
* Doxygenlloyd2010-06-211-9/+9
* More Doxygen updates/fixeslloyd2010-06-151-0/+3
* Use "/*" instead of "/**" in starting comments at the begining of a file.lloyd2010-06-071-1/+1
* Remove stubs for VIA Padlock support. I have no plans to implement itlloyd2010-01-051-7/+1
* Add missing BOTAN_DLL exports.lloyd2009-12-161-1/+1
* Rename CPUID::has_intel_aes to has_aes_intel, and add CPUID::has_aes_via,lloyd2009-11-101-2/+11
* Add CPUID::have_altivec for AltiVec runtime detection.lloyd2009-10-291-0/+1
* Add cpuid check for Intel AESlloyd2009-09-301-1/+8
* Significantly rework CPUID support. Add cache line detectionlloyd2009-09-291-26/+42
* Add runtime cpuid support. Check in the SSE2 engine that SSE2 is actuallylloyd2009-09-251-0/+51