diff options
| -rwxr-xr-x | configure.py | 15 | ||||
| -rw-r--r-- | src/build-data/arch/ia32.txt | 1 | ||||
| -rw-r--r-- | src/build-data/cc/gcc.txt | 1 |
3 files changed, 9 insertions, 8 deletions
diff --git a/configure.py b/configure.py index a4fa0e27f..acb0f267c 100755 --- a/configure.py +++ b/configure.py @@ -160,7 +160,7 @@ def process_command_line(args): dest='unaligned_mem', action='store_false', help=SUPPRESS_HELP) - for isa_extn_name in ['SSE2', 'SSSE3', 'AltiVec', 'AES-NI']: + for isa_extn_name in ['SSE2', 'SSSE3', 'AltiVec', 'AES-NI', 'movbe']: isa_extn = isa_extn_name.lower() target_group.add_option('--enable-%s' % (isa_extn), @@ -348,9 +348,10 @@ def process_command_line(args): options.disable_isa_extns.append(isa) for isa in options.enable_isa_extns: - for dep in isa_deps.get(isa, '').split(','): - if not enabled_or_disabled_isa(dep): - options.enable_isa_extns.append(dep) + if isa in isa_deps: + for dep in isa_deps.get(isa, '').split(','): + if not enabled_or_disabled_isa(dep): + options.enable_isa_extns.append(dep) return options @@ -609,10 +610,8 @@ class ArchInfo(object): if self.basename != options.cpu: macros.append('TARGET_CPU_IS_%s' % (form_macro(options.cpu))) - enabled_isas = set(flatten( - [self.isa_extensions_in(options.cpu), - options.enable_isa_extns])) - + enabled_isas = set(self.isa_extensions_in(options.cpu) + + options.enable_isa_extns) disabled_isas = set(options.disable_isa_extns) isa_extensions = sorted(enabled_isas - disabled_isas) diff --git a/src/build-data/arch/ia32.txt b/src/build-data/arch/ia32.txt index d9b09746d..c2d4d1769 100644 --- a/src/build-data/arch/ia32.txt +++ b/src/build-data/arch/ia32.txt @@ -61,4 +61,5 @@ intelcput2700 -> prescott <isa_extn> sse2:pentium4,prescott,pentium-m,atom ssse3:atom +movbe:atom </isa_extn> diff --git a/src/build-data/cc/gcc.txt b/src/build-data/cc/gcc.txt index 2eef94726..c60b9c6bb 100644 --- a/src/build-data/cc/gcc.txt +++ b/src/build-data/cc/gcc.txt @@ -47,6 +47,7 @@ ppc601 -> "-mpowerpc -mcpu=601" # Until GCC gets -march support for these models nehalem -> "-march=core2 -msse4.1 -msse4.2" westmere -> "-march=core2 -maes -msse4.1 -msse4.2" +atom -> "-march=i686 -msse2 -mssse3" cellppu -> "" alpha-ev68 -> "-mcpu=ev6" alpha-ev7 -> "-mcpu=ev6" |