diff options
| -rw-r--r-- | src/build-data/buildh.in | 11 | ||||
| -rw-r--r-- | src/lib/utils/cpuid.cpp | 2 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/build-data/buildh.in b/src/build-data/buildh.in index 49ef89146..8b950177f 100644 --- a/src/build-data/buildh.in +++ b/src/build-data/buildh.in @@ -184,6 +184,17 @@ #define BOTAN_TARGET_CPU_HAS_KNOWN_ENDIANNESS #endif +/* +* If no way of dynamically determining the cache line size for the +* system exists, this value is used as the default. Used by the side +* channel countermeasures rather than for alignment purposes, so it is +* better to be on the smaller side if the exact value cannot be +* determined. Typically 32 or 64 bytes on modern CPUs. +*/ +#if !defined(BOTAN_TARGET_CPU_DEFAULT_CACHE_LINE_SIZE) + #define BOTAN_TARGET_CPU_DEFAULT_CACHE_LINE_SIZE 32 +#endif + %{target_compiler_defines} #if defined(_MSC_VER) diff --git a/src/lib/utils/cpuid.cpp b/src/lib/utils/cpuid.cpp index c98829789..695a28550 100644 --- a/src/lib/utils/cpuid.cpp +++ b/src/lib/utils/cpuid.cpp @@ -74,7 +74,7 @@ namespace Botan { u64bit CPUID::g_x86_processor_flags[2] = { 0, 0 }; -size_t CPUID::g_cache_line_size = 0; +size_t CPUID::g_cache_line_size = BOTAN_TARGET_CPU_DEFAULT_CACHE_LINE_SIZE; bool CPUID::g_altivec_capable = false; bool CPUID::g_initialized = false; |