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The 5.0 kernel defines the macro ASM_BUG. In order to prevent a
conflict and build failure rename ASM_BUG to ZFS_ASM_BUG. This
is currently only an issue on aarch64 but all instances of
ASM_BUG we're renamed to avoid any future conflict on x86_64.
Reviewed-by: Tomohiro Kusumi <[email protected]>
Reviewed-by: Richard Laager <[email protected]>
Reviewed-by: Chris Dunlop <[email protected]>
Signed-off-by: Brian Behlendorf <[email protected]>
Closes #8725
Issue #8545
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Implement shift based multiplication for 512f. Higher IPC over lookup based
methods yields up to 40% better performance on the current hardware.
Results on Xeon Phi(TM) CPU 7210:
implementation gen_p gen_pq gen_pqr rec_p rec_q rec_r rec_pq rec_pr rec_qr rec_pqr
original 142232671 24411492 12948205 283053705 22348167 4215911 9171609 2265548 2378370 1648495
scalar 295711162 49851491 33253815 293198109 88179448 61866752 27941684 25764416 17384442 12138153
sse2 410055998 199642658 117973654 406240463 152688682 121092250 84968180 79291076 47473657 20779719
ssse3 411641595 199669571 117937647 406211024 137638508 117050346 81263322 76120405 46281559 32696722
avx2 616485806 311515332 188595628 605455115 260602390 230554476 148198817 138800254 92273356 62937819
avx512f 832191523 408509425 253599522 810094481 404325734 317590971 218235687 197204920 133101937 94001219
fastest avx512f avx512f avx512f avx512f avx512f avx512f avx512f avx512f avx512f avx512f
Signed-off-by: Gvozden Neskovic <[email protected]>
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Enable vectorized raidz code on ABD buffers. The avx512f,
avx512bw, neon and aarch64_neonx2 are disabled in this commit.
With the exception of avx512bw these implementations are
updated for ABD in the subsequent commits.
Signed-off-by: Gvozden Neskovic <[email protected]>
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This re-use the framework established for SSE2, SSSE3 and
AVX2. However, GCC is using FP registers on Aarch64, so
unlike SSE/AVX2 we can't rely on the registers being left alone
between ASM statements. So instead, the NEON code uses
C variables and GCC extended ASM syntax. Note that since
the kernel explicitly disable vector registers, they
have to be locally re-enabled explicitly.
As we use the variable's number to define the symbolic
name, and GCC won't allow duplicate symbolic names,
numbers have to be unique. Even when the code is not
going to be used (e.g. the case for 4 registers when
using the macro with only 2). Only the actually used
variables should be declared, otherwise the build
will fails in debug mode.
This requires the replacement of the XOR(X,X) syntax
by a new ZERO(X) macro, which does the same thing but
without repeating the argument. And perhaps someday
there will be a machine where there is a more efficient
way to zero a register than XOR with itself. This affects
scalar, SSE2, SSSE3 and AVX2 as they need the new macro.
It's possible to write faster implementations (different
scheduling, different unrolling, interleaving NEON and
scalar, ...) for various cores, but this one has the
advantage of fitting in the current state of the code,
and thus is likely easier to review/check/merge.
The only difference between aarch64-neon and aarch64-neonx2
is that aarch64-neonx2 unroll some functions some more.
Reviewed-by: Gvozden Neskovic <[email protected]>
Reviewed-by: Brian Behlendorf <[email protected]>
Signed-off-by: Romain Dolbeau <[email protected]>
Closes #4801
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- Implementation lock replaced with atomic variable
- Trailing whitespace is removed from user specified parameter, to enhance
experience when using commands that add newline, e.g. `echo`
- raidz_test: remove dependency on `getrusage()` and RUSAGE_THREAD, Issue #4813
- silence `cppcheck` in vdev_raidz, partial solution of Issue #1392
- Minor fixes and cleanups
- Enable use of original parity methods in [fastest] configuration.
New opaque original ops structure, representing native methods, is added
to supported raidz methods. Original parity methods are executed if selected
implementation has NULL fn pointer.
Signed-off-by: Gvozden Neskovic <[email protected]>
Signed-off-by: Brian Behlendorf <[email protected]>
Issue #4813
Issue #1392
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The patch covers low-end and older x86 CPUs. Parity generation is
equivalent to SSSE3 implementation, but reconstruction is somewhat
slower. Previous 'sse' implementation is renamed to 'ssse3' to
indicate highest instruction set used.
Benchmark results:
scalar_rec_p 4 720476442
scalar_rec_q 4 187462804
scalar_rec_r 4 138996096
scalar_rec_pq 4 140834951
scalar_rec_pr 4 129332035
scalar_rec_qr 4 81619194
scalar_rec_pqr 4 53376668
sse2_rec_p 4 2427757064
sse2_rec_q 4 747120861
sse2_rec_r 4 499871637
sse2_rec_pq 4 522403710
sse2_rec_pr 4 464632780
sse2_rec_qr 4 319124434
sse2_rec_pqr 4 205794190
ssse3_rec_p 4 2519939444
ssse3_rec_q 4 1003019289
ssse3_rec_r 4 616428767
ssse3_rec_pq 4 706326396
ssse3_rec_pr 4 570493618
ssse3_rec_qr 4 400185250
ssse3_rec_pqr 4 377541245
original_rec_p 4 691658568
original_rec_q 4 195510948
original_rec_r 4 26075538
original_rec_pq 4 103087368
original_rec_pr 4 15767058
original_rec_qr 4 15513175
original_rec_pqr 4 10746357
Signed-off-by: Gvozden Neskovic <[email protected]>
Signed-off-by: Brian Behlendorf <[email protected]>
Closes #4783
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