diff options
| author | Romain Dolbeau <[email protected]> | 2016-11-04 18:53:03 +0100 |
|---|---|---|
| committer | Brian Behlendorf <[email protected]> | 2016-11-04 10:53:03 -0700 |
| commit | 7f3194932d22c667026aff1b263ceaa1ebd012ee (patch) | |
| tree | b68eee7abd34de2410db38208c35c184af2ddd70 /module/zcommon/zfs_fletcher_aarch64_neon.c | |
| parent | ace1eae84cca8579596f46262d99df19f6d7e963 (diff) | |
Add superscalar fletcher4
This is the Fletcher4 algorithm implemented in pure C, but using
multiple counters using algorithms identical to those used for
SSE/NEON and AVX2.
This allows for faster execution on core with strong superscalar
capabilities but weak SIMD capabilities.
Reviewed-by: Brian Behlendorf <[email protected]>
Signed-off-by: Romain Dolbeau <[email protected]>
Closes #5317
Diffstat (limited to 'module/zcommon/zfs_fletcher_aarch64_neon.c')
| -rw-r--r-- | module/zcommon/zfs_fletcher_aarch64_neon.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/module/zcommon/zfs_fletcher_aarch64_neon.c b/module/zcommon/zfs_fletcher_aarch64_neon.c index f8991b171..b72c1bafd 100644 --- a/module/zcommon/zfs_fletcher_aarch64_neon.c +++ b/module/zcommon/zfs_fletcher_aarch64_neon.c @@ -2,7 +2,7 @@ * Implement fast Fletcher4 with NEON instructions. (aarch64) * * Use the 128-bit NEON SIMD instructions and registers to compute - * Fletcher4 in four incremental 64-bit parallel accumulator streams, + * Fletcher4 in two incremental 64-bit parallel accumulator streams, * and then combine the streams to form the final four checksum words. * This implementation is a derivative of the AVX SIMD implementation by * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c). |