Fix spelling

Reviewed-by: Brian Behlendorf <[email protected]
Reviewed-by: Giuseppe Di Natale <[email protected]>>
Reviewed-by: George Melikov <[email protected]>
Reviewed-by: Haakan T Johansson <[email protected]>
Closes #5547 
Closes #5543 

5 files changed, 5 insertions, 5 deletions

diff --git a/module/icp/asm-x86_64/sha2/sha256_impl.S b/module/icp/asm-x86_64/sha2/sha256_impl.S
index d55c5eb48..367795668 100644
--- a/module/icp/asm-x86_64/sha2/sha256_impl.S
+++ b/module/icp/asm-x86_64/sha2/sha256_impl.S
@@ -33,7 +33,7 @@
  * level parallelism, on a given CPU implementation in this case.
  *
  * Special note on Intel EM64T. While Opteron CPU exhibits perfect
- * perfromance ratio of 1.5 between 64- and 32-bit flavors [see above],
+ * performance ratio of 1.5 between 64- and 32-bit flavors [see above],
  * [currently available] EM64T CPUs apparently are far from it. On the
  * contrary, 64-bit version, sha512_block, is ~30% *slower* than 32-bit
  * sha256_block:-( This is presumably because 64-bit shifts/rotates
diff --git a/module/icp/asm-x86_64/sha2/sha512_impl.S b/module/icp/asm-x86_64/sha2/sha512_impl.S
index 248d8b2cc..5a49cff4b 100644
--- a/module/icp/asm-x86_64/sha2/sha512_impl.S
+++ b/module/icp/asm-x86_64/sha2/sha512_impl.S
@@ -33,7 +33,7 @@
  * level parallelism, on a given CPU implementation in this case.
  *
  * Special note on Intel EM64T. While Opteron CPU exhibits perfect
- * perfromance ratio of 1.5 between 64- and 32-bit flavors [see above],
+ * performance ratio of 1.5 between 64- and 32-bit flavors [see above],
  * [currently available] EM64T CPUs apparently are far from it. On the
  * contrary, 64-bit version, sha512_block, is ~30% *slower* than 32-bit
  * sha256_block:-( This is presumably because 64-bit shifts/rotates
diff --git a/module/icp/core/kcf_callprov.c b/module/icp/core/kcf_callprov.c
index 38927dcc0..fd2f7e1aa 100644
--- a/module/icp/core/kcf_callprov.c
+++ b/module/icp/core/kcf_callprov.c
@@ -282,7 +282,7 @@ kcf_get_mech_provider(crypto_mech_type_t mech_type, kcf_mech_entry_t **mepp,
 	prov_chain = me->me_hw_prov_chain;
 
 	/*
-	 * We check for the threshhold for using a hardware provider for
+	 * We check for the threshold for using a hardware provider for
 	 * this amount of data. If there is no software provider available
 	 * for the mechanism, then the threshold is ignored.
 	 */
diff --git a/module/icp/core/kcf_mech_tabs.c b/module/icp/core/kcf_mech_tabs.c
index 3ed154758..cac34a44a 100644
--- a/module/icp/core/kcf_mech_tabs.c
+++ b/module/icp/core/kcf_mech_tabs.c
@@ -100,7 +100,7 @@ kcf_mech_entry_tab_t kcf_mech_tabs_tab[KCF_LAST_OPSCLASS + 1] = {
 };
 
 /*
- * Per-algorithm internal threasholds for the minimum input size of before
+ * Per-algorithm internal thresholds for the minimum input size of before
  * offloading to hardware provider.
  * Dispatching a crypto operation  to a hardware provider entails paying the
  * cost of an additional context switch.  Measurments with Sun Accelerator 4000
diff --git a/module/icp/include/sha1/sha1.h b/module/icp/include/sha1/sha1.h
index b6ae6b8d2..251b64fca 100644
--- a/module/icp/include/sha1/sha1.h
+++ b/module/icp/include/sha1/sha1.h
@@ -35,7 +35,7 @@ extern "C" {
 /*
  * NOTE: n2rng (Niagara2 RNG driver) accesses the state field of
  * SHA1_CTX directly.  NEVER change this structure without verifying
- * compatiblity with n2rng.  The important thing is that the state
+ * compatibility with n2rng.  The important thing is that the state
  * must be in a field declared as uint32_t state[5].
  */
 /* SHA-1 context. */