diff options
| author | Brian Behlendorf <[email protected]> | 2019-07-16 17:22:31 -0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-07-16 17:22:31 -0700 |
| commit | 8062b7686aa2c3a22824b9a7c83cf01a5fa457a0 (patch) | |
| tree | e7e316a0cdadec44f3d6bde7adaf917dccdd6370 /include/linux | |
| parent | 3b03ff22761da0f5fad9a781025facfc6e555522 (diff) | |
Minor style cleanup
Resolve an assortment of style inconsistencies including
use of white space, typos, capitalization, and line wrapping.
There is no functional change.
Reviewed-by: Tony Hutter <[email protected]>
Reviewed-by: George Melikov <[email protected]>
Signed-off-by: Brian Behlendorf <[email protected]>
Closes #9030
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/simd_aarch64.h | 6 | ||||
| -rw-r--r-- | include/linux/simd_x86.h | 48 |
2 files changed, 29 insertions, 25 deletions
diff --git a/include/linux/simd_aarch64.h b/include/linux/simd_aarch64.h index 1cfcd01e4..b45d31c48 100644 --- a/include/linux/simd_aarch64.h +++ b/include/linux/simd_aarch64.h @@ -26,8 +26,10 @@ * USER API: * * Kernel fpu methods: - * kfpu_begin() - * kfpu_end() + * kfpu_allowed() + * kfpu_initialize() + * kfpu_begin() + * kfpu_end() */ #ifndef _SIMD_AARCH64_H diff --git a/include/linux/simd_x86.h b/include/linux/simd_x86.h index 2d7a1c3a5..641f43955 100644 --- a/include/linux/simd_x86.h +++ b/include/linux/simd_x86.h @@ -26,8 +26,10 @@ * USER API: * * Kernel fpu methods: - * kfpu_begin() - * kfpu_end() + * kfpu_allowed() + * kfpu_initialize() + * kfpu_begin() + * kfpu_end() * * SIMD support: * @@ -37,31 +39,31 @@ * all relevant feature test functions should be called. * * Supported features: - * zfs_sse_available() - * zfs_sse2_available() - * zfs_sse3_available() - * zfs_ssse3_available() - * zfs_sse4_1_available() - * zfs_sse4_2_available() + * zfs_sse_available() + * zfs_sse2_available() + * zfs_sse3_available() + * zfs_ssse3_available() + * zfs_sse4_1_available() + * zfs_sse4_2_available() * - * zfs_avx_available() - * zfs_avx2_available() + * zfs_avx_available() + * zfs_avx2_available() * - * zfs_bmi1_available() - * zfs_bmi2_available() + * zfs_bmi1_available() + * zfs_bmi2_available() * - * zfs_avx512f_available() - * zfs_avx512cd_available() - * zfs_avx512er_available() - * zfs_avx512pf_available() - * zfs_avx512bw_available() - * zfs_avx512dq_available() - * zfs_avx512vl_available() - * zfs_avx512ifma_available() - * zfs_avx512vbmi_available() + * zfs_avx512f_available() + * zfs_avx512cd_available() + * zfs_avx512er_available() + * zfs_avx512pf_available() + * zfs_avx512bw_available() + * zfs_avx512dq_available() + * zfs_avx512vl_available() + * zfs_avx512ifma_available() + * zfs_avx512vbmi_available() * * NOTE(AVX-512VL): If using AVX-512 instructions with 128Bit registers - * also add zfs_avx512vl_available() to feature check. + * also add zfs_avx512vl_available() to feature check. */ #ifndef _SIMD_X86_H @@ -292,7 +294,7 @@ typedef struct cpuid_feature_desc { * Descriptions of supported instruction sets */ static const cpuid_feature_desc_t cpuid_features[] = { - [SSE] = {1U, 0U, 1U << 25, EDX }, + [SSE] = {1U, 0U, 1U << 25, EDX }, [SSE2] = {1U, 0U, 1U << 26, EDX }, [SSE3] = {1U, 0U, 1U << 0, ECX }, [SSSE3] = {1U, 0U, 1U << 9, ECX }, |