1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
|
/*
* Copyright (c) 2014 Scott Mansell
* Copyright © 2014 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include <stdio.h>
#include <inttypes.h>
#include "pipe/p_state.h"
#include "util/u_format.h"
#include "util/u_hash_table.h"
#include "util/u_hash.h"
#include "util/u_memory.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_dump.h"
#include "vc4_context.h"
#include "vc4_qpu.h"
#include "vc4_qir.h"
#ifdef USE_VC4_SIMULATOR
#include "simpenrose/simpenrose.h"
#endif
struct tgsi_to_qir {
struct tgsi_parse_context parser;
struct qcompile *c;
struct qreg *temps;
struct qreg *inputs;
struct qreg *outputs;
struct qreg *uniforms;
struct qreg *consts;
uint32_t num_consts;
struct pipe_shader_state *shader_state;
struct vc4_fs_key *fs_key;
struct vc4_vs_key *vs_key;
uint32_t *uniform_data;
enum quniform_contents *uniform_contents;
uint32_t num_uniforms;
uint32_t num_outputs;
};
struct vc4_key {
struct pipe_shader_state *shader_state;
};
struct vc4_fs_key {
struct vc4_key base;
enum pipe_format color_format;
};
struct vc4_vs_key {
struct vc4_key base;
enum pipe_format attr_formats[8];
};
static struct qreg
add_uniform(struct tgsi_to_qir *trans,
enum quniform_contents contents,
uint32_t data)
{
uint32_t uniform = trans->num_uniforms++;
struct qreg u = { QFILE_UNIF, uniform };
trans->uniform_contents[uniform] = contents;
trans->uniform_data[uniform] = data;
return u;
}
static struct qreg
get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
uint32_t data)
{
struct qcompile *c = trans->c;
for (int i = 0; i < trans->num_uniforms; i++) {
if (trans->uniform_contents[i] == contents &&
trans->uniform_data[i] == data)
return trans->uniforms[i];
}
struct qreg u = add_uniform(trans, contents, data);
struct qreg t = qir_MOV(c, u);
trans->uniforms[u.index] = t;
return t;
}
static struct qreg
qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
{
return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
}
static struct qreg
qir_uniform_f(struct tgsi_to_qir *trans, float f)
{
return qir_uniform_ui(trans, fui(f));
}
static struct qreg
get_src(struct tgsi_to_qir *trans, struct tgsi_src_register *src, int i)
{
struct qcompile *c = trans->c;
struct qreg r = c->undef;
uint32_t s = i;
switch (i) {
case TGSI_SWIZZLE_X:
s = src->SwizzleX;
break;
case TGSI_SWIZZLE_Y:
s = src->SwizzleY;
break;
case TGSI_SWIZZLE_Z:
s = src->SwizzleZ;
break;
case TGSI_SWIZZLE_W:
s = src->SwizzleW;
break;
default:
abort();
}
assert(!src->Indirect);
switch (src->File) {
case TGSI_FILE_NULL:
return r;
case TGSI_FILE_TEMPORARY:
r = trans->temps[src->Index * 4 + s];
break;
case TGSI_FILE_IMMEDIATE:
r = trans->consts[src->Index * 4 + s];
break;
case TGSI_FILE_CONSTANT:
r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
src->Index * 4 + s);
break;
case TGSI_FILE_INPUT:
r = trans->inputs[src->Index * 4 + s];
break;
case TGSI_FILE_SAMPLER:
case TGSI_FILE_SAMPLER_VIEW:
r = c->undef;
break;
default:
fprintf(stderr, "unknown src file %d\n", src->File);
abort();
}
if (src->Absolute)
r = qir_FMAXABS(c, r, r);
if (src->Negate)
r = qir_FSUB(c, qir_uniform_f(trans, 0), r);
return r;
};
static void
update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
int i, struct qreg val)
{
struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
assert(!tgsi_dst->Indirect);
switch (tgsi_dst->File) {
case TGSI_FILE_TEMPORARY:
trans->temps[tgsi_dst->Index * 4 + i] = val;
break;
case TGSI_FILE_OUTPUT:
trans->outputs[tgsi_dst->Index * 4 + i] = val;
trans->num_outputs = MAX2(trans->num_outputs,
tgsi_dst->Index * 4 + i + 1);
break;
default:
fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
abort();
}
};
static struct qreg
tgsi_to_qir_alu(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
struct qreg dst = qir_get_temp(c);
qir_emit(c, qir_inst4(op, dst,
src[0 * 4 + i],
src[1 * 4 + i],
src[2 * 4 + i],
c->undef));
return dst;
}
static struct qreg
tgsi_to_qir_mad(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
return qir_FADD(c,
qir_FMUL(c,
src[0 * 4 + i],
src[1 * 4 + i]),
src[2 * 4 + i]);
}
static struct qreg
tgsi_to_qir_lit(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
struct qreg x = src[0 * 4 + 0];
struct qreg y = src[0 * 4 + 1];
struct qreg w = src[0 * 4 + 3];
switch (i) {
case 0:
case 3:
return qir_uniform_f(trans, 1.0);
case 1:
return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
case 2: {
struct qreg zero = qir_uniform_f(trans, 0.0);
/* XXX: Clamp w to -128..128 */
return qir_CMP(c,
x,
zero,
qir_EXP2(c, qir_FMUL(c,
w,
qir_LOG2(c,
qir_FMAX(c,
y,
zero)))));
}
default:
assert(!"not reached");
return c->undef;
}
}
static struct qreg
tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
struct qreg src0 = src[0 * 4 + i];
struct qreg src1 = src[1 * 4 + i];
struct qreg src2 = src[2 * 4 + i];
/* LRP is:
* src0 * src1 + (1 - src0) * src2.
* -> src0 * src1 + src2 - src0 * src2
* -> src2 + src0 * (src1 - src2)
*/
return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
}
static void
tgsi_to_qir_tex(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src)
{
struct qcompile *c = trans->c;
assert(!tgsi_inst->Instruction.Saturate);
struct qreg s = src[0 * 4 + 0];
struct qreg t = src[0 * 4 + 1];
if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
s = qir_FMUL(c, s, proj);
t = qir_FMUL(c, t, proj);
}
/* There is no native support for GL texture rectangle coordinates, so
* we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
* 1]).
*/
if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
uint32_t sampler = 0; /* XXX */
s = qir_FMUL(c, s,
get_temp_for_uniform(trans,
QUNIFORM_TEXRECT_SCALE_X,
sampler));
t = qir_FMUL(c, t,
get_temp_for_uniform(trans,
QUNIFORM_TEXRECT_SCALE_Y,
sampler));
}
uint32_t tex_and_sampler = 0; /* XXX */
qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
tex_and_sampler));
struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
tex_and_sampler);
if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
} else {
qir_TEX_S(c, s, sampler_p1);
}
qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
for (int i = 0; i < 4; i++) {
if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
continue;
struct qreg dst = qir_get_temp(c);
qir_emit(c, qir_inst(QOP_R4_UNPACK_A + i,
dst,
c->undef, c->undef));
update_dst(trans, tgsi_inst, i, dst);
}
}
static struct qreg
tgsi_to_qir_pow(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
/* Note that this instruction replicates its result from the x channel
*/
return qir_EXP2(c, qir_FMUL(c,
src[1 * 4 + 0],
qir_LOG2(c, src[0 * 4 + 0])));
}
static struct qreg
tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
}
/**
* Computes x - floor(x), which is tricky because our FTOI truncates (rounds
* to zero).
*/
static struct qreg
tgsi_to_qir_frc(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
return qir_CMP(c,
diff,
qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
diff);
}
static struct qreg
tgsi_to_qir_dp(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
int num, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
for (int j = 1; j < num; j++) {
sum = qir_FADD(c, sum, qir_FMUL(c,
src[0 * 4 + j],
src[1 * 4 + j]));
}
return sum;
}
static struct qreg
tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
}
static struct qreg
tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
}
static struct qreg
tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
}
static struct qreg
tgsi_to_qir_abs(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
struct qreg arg = src[0 * 4 + i];
return qir_FMAXABS(c, arg, arg);
}
/* Note that this instruction replicates its result from the x channel */
static struct qreg
tgsi_to_qir_sin(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
float coeff[] = {
2.0 * M_PI,
-pow(2.0 * M_PI, 3) / (3 * 2 * 1),
pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
-pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
};
struct qreg scaled_x =
qir_FMUL(c,
src[0 * 4 + 0],
qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
struct qreg x2 = qir_FMUL(c, x, x);
struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
x = qir_FMUL(c, x, x2);
sum = qir_FADD(c,
sum,
qir_FMUL(c,
x,
qir_uniform_f(trans, coeff[i])));
}
return sum;
}
/* Note that this instruction replicates its result from the x channel */
static struct qreg
tgsi_to_qir_cos(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op, struct qreg *src, int i)
{
struct qcompile *c = trans->c;
float coeff[] = {
1.0f,
-pow(2.0 * M_PI, 2) / (2 * 1),
pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
-pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
};
struct qreg scaled_x =
qir_FMUL(c, src[0 * 4 + 0],
qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
struct qreg sum = qir_uniform_f(trans, coeff[0]);
struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
struct qreg x = x2; /* Current x^2, x^4, or x^6 */
for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
if (i != 1)
x = qir_FMUL(c, x, x2);
struct qreg mul = qir_FMUL(c,
x,
qir_uniform_f(trans, coeff[i]));
if (i == 0)
sum = mul;
else
sum = qir_FADD(c, sum, mul);
}
return sum;
}
static void
emit_vertex_input(struct tgsi_to_qir *trans, int attr)
{
enum pipe_format format = trans->vs_key->attr_formats[attr];
struct qcompile *c = trans->c;
struct qreg vpm_reads[4];
/* Right now, we're setting the VPM offsets to be 16 bytes wide every
* time, so we always read 4 32-bit VPM entries.
*/
for (int i = 0; i < 4; i++) {
vpm_reads[i] = qir_get_temp(c);
qir_emit(c, qir_inst(QOP_VPM_READ,
vpm_reads[i],
c->undef,
c->undef));
c->num_inputs++;
}
bool format_warned = false;
const struct util_format_description *desc =
util_format_description(format);
for (int i = 0; i < 4; i++) {
uint8_t swiz = desc->swizzle[i];
switch (swiz) {
case UTIL_FORMAT_SWIZZLE_NONE:
if (!format_warned) {
fprintf(stderr,
"vtx element %d NONE swizzle: %s\n",
attr, util_format_name(format));
format_warned = true;
}
/* FALLTHROUGH */
case UTIL_FORMAT_SWIZZLE_0:
trans->inputs[attr * 4 + i] = qir_uniform_ui(trans, 0);
break;
case UTIL_FORMAT_SWIZZLE_1:
trans->inputs[attr * 4 + i] = qir_uniform_ui(trans,
fui(1.0));
break;
default:
if (!format_warned &&
(desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
desc->channel[swiz].size != 32)) {
fprintf(stderr,
"vtx element %d unsupported type: %s\n",
attr, util_format_name(format));
format_warned = true;
}
trans->inputs[attr * 4 + i] = vpm_reads[swiz];
break;
}
}
}
static void
emit_tgsi_declaration(struct tgsi_to_qir *trans,
struct tgsi_full_declaration *decl)
{
struct qcompile *c = trans->c;
switch (decl->Declaration.File) {
case TGSI_FILE_INPUT:
if (c->stage == QSTAGE_FRAG) {
for (int i = decl->Range.First * 4;
i < (decl->Range.Last + 1) * 4;
i++) {
struct qreg vary = {
QFILE_VARY,
i
};
trans->inputs[i] =
qir_VARY_ADD_C(c, qir_MOV(c, vary));
c->num_inputs++;
}
} else {
for (int i = decl->Range.First;
i <= decl->Range.Last;
i++) {
emit_vertex_input(trans, i);
}
}
break;
}
}
static void
emit_tgsi_instruction(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst)
{
struct qcompile *c = trans->c;
struct {
enum qop op;
struct qreg (*func)(struct tgsi_to_qir *trans,
struct tgsi_full_instruction *tgsi_inst,
enum qop op,
struct qreg *src, int i);
} op_trans[] = {
[TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
[TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
[TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
[TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
[TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
[TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
[TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
[TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
[TGSI_OPCODE_SEQ] = { QOP_SEQ, tgsi_to_qir_alu },
[TGSI_OPCODE_SNE] = { QOP_SNE, tgsi_to_qir_alu },
[TGSI_OPCODE_SGE] = { QOP_SGE, tgsi_to_qir_alu },
[TGSI_OPCODE_SLT] = { QOP_SLT, tgsi_to_qir_alu },
[TGSI_OPCODE_CMP] = { QOP_CMP, tgsi_to_qir_alu },
[TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
[TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
[TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
[TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
[TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
[TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
[TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
[TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
[TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
[TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
[TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
[TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
[TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
[TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
[TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
};
static int asdf = 0;
uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
if (tgsi_op == TGSI_OPCODE_END)
return;
struct qreg src_regs[12];
for (int s = 0; s < 3; s++) {
for (int i = 0; i < 4; i++) {
src_regs[4 * s + i] =
get_src(trans, &tgsi_inst->Src[s].Register, i);
}
}
switch (tgsi_op) {
case TGSI_OPCODE_TEX:
case TGSI_OPCODE_TXP:
case TGSI_OPCODE_TXB:
tgsi_to_qir_tex(trans, tgsi_inst,
op_trans[tgsi_op].op, src_regs);
return;
default:
break;
}
if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
fprintf(stderr, "unknown tgsi inst: ");
tgsi_dump_instruction(tgsi_inst, asdf++);
fprintf(stderr, "\n");
abort();
}
for (int i = 0; i < 4; i++) {
if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
continue;
struct qreg result;
result = op_trans[tgsi_op].func(trans, tgsi_inst,
op_trans[tgsi_op].op,
src_regs, i);
if (tgsi_inst->Instruction.Saturate) {
float low = (tgsi_inst->Instruction.Saturate ==
TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
result = qir_FMAX(c,
qir_FMIN(c,
result,
qir_uniform_f(trans, 1.0)),
qir_uniform_f(trans, low));
}
update_dst(trans, tgsi_inst, i, result);
}
}
static void
parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
{
for (int i = 0; i < 4; i++) {
unsigned n = trans->num_consts++;
trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
}
}
static void
emit_frag_end(struct tgsi_to_qir *trans)
{
struct qcompile *c = trans->c;
struct qreg t = qir_get_temp(c);
const struct util_format_description *format_desc =
util_format_description(trans->fs_key->color_format);
/* Debug: Sometimes you're getting a black output and just want to see
* if the FS is getting executed at all. Spam magenta into the color
* output.
*/
if (0) {
trans->outputs[format_desc->swizzle[0]] =
qir_uniform_ui(trans, fui(1.0));
trans->outputs[format_desc->swizzle[1]] =
qir_uniform_ui(trans, fui(0.0));
trans->outputs[format_desc->swizzle[2]] =
qir_uniform_ui(trans, fui(1.0));
trans->outputs[format_desc->swizzle[3]] =
qir_uniform_ui(trans, fui(0.5));
}
struct qreg swizzled_outputs[4] = {
trans->outputs[format_desc->swizzle[0]],
trans->outputs[format_desc->swizzle[1]],
trans->outputs[format_desc->swizzle[2]],
trans->outputs[format_desc->swizzle[3]],
};
qir_emit(c, qir_inst4(QOP_PACK_COLORS, t,
swizzled_outputs[0],
swizzled_outputs[1],
swizzled_outputs[2],
swizzled_outputs[3]));
qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
t, c->undef));
}
static void
emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
{
struct qcompile *c = trans->c;
struct qreg xyi[2];
for (int i = 0; i < 2; i++) {
struct qreg scale =
add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
xyi[i] = qir_FTOI(c, qir_FMUL(c,
qir_FMUL(c,
trans->outputs[i],
scale),
rcp_w));
}
qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
}
static void
emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
{
struct qcompile *c = trans->c;
qir_VPM_WRITE(c, qir_FMUL(c, trans->outputs[2], rcp_w));
}
static void
emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
{
struct qcompile *c = trans->c;
qir_VPM_WRITE(c, rcp_w);
}
static void
emit_vert_end(struct tgsi_to_qir *trans)
{
struct qcompile *c = trans->c;
struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
emit_scaled_viewport_write(trans, rcp_w);
emit_zs_write(trans, rcp_w);
emit_rcp_wc_write(trans, rcp_w);
for (int i = 4; i < trans->num_outputs; i++) {
qir_VPM_WRITE(c, trans->outputs[i]);
}
}
static void
emit_coord_end(struct tgsi_to_qir *trans)
{
struct qcompile *c = trans->c;
struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
for (int i = 0; i < 4; i++)
qir_VPM_WRITE(c, trans->outputs[i]);
emit_scaled_viewport_write(trans, rcp_w);
emit_zs_write(trans, rcp_w);
emit_rcp_wc_write(trans, rcp_w);
}
static struct tgsi_to_qir *
vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
struct vc4_key *key)
{
struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
struct qcompile *c;
int ret;
c = qir_compile_init();
c->stage = stage;
memset(trans, 0, sizeof(*trans));
/* XXX sizing */
trans->temps = calloc(sizeof(struct qreg), 1024);
trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
trans->outputs = calloc(sizeof(struct qreg), 1024);
trans->uniforms = calloc(sizeof(struct qreg), 1024);
trans->consts = calloc(sizeof(struct qreg), 1024);
trans->uniform_data = calloc(sizeof(uint32_t), 1024);
trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
trans->shader_state = key->shader_state;
trans->c = c;
ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
assert(ret == TGSI_PARSE_OK);
if (vc4_debug & VC4_DEBUG_TGSI) {
fprintf(stderr, "TGSI:\n");
tgsi_dump(trans->shader_state->tokens, 0);
}
switch (stage) {
case QSTAGE_FRAG:
trans->fs_key = (struct vc4_fs_key *)key;
break;
case QSTAGE_VERT:
trans->vs_key = (struct vc4_vs_key *)key;
break;
case QSTAGE_COORD:
trans->vs_key = (struct vc4_vs_key *)key;
break;
}
while (!tgsi_parse_end_of_tokens(&trans->parser)) {
tgsi_parse_token(&trans->parser);
switch (trans->parser.FullToken.Token.Type) {
case TGSI_TOKEN_TYPE_DECLARATION:
emit_tgsi_declaration(trans,
&trans->parser.FullToken.FullDeclaration);
break;
case TGSI_TOKEN_TYPE_INSTRUCTION:
emit_tgsi_instruction(trans,
&trans->parser.FullToken.FullInstruction);
break;
case TGSI_TOKEN_TYPE_IMMEDIATE:
parse_tgsi_immediate(trans,
&trans->parser.FullToken.FullImmediate);
break;
}
}
switch (stage) {
case QSTAGE_FRAG:
emit_frag_end(trans);
break;
case QSTAGE_VERT:
emit_vert_end(trans);
break;
case QSTAGE_COORD:
emit_coord_end(trans);
break;
}
tgsi_parse_free(&trans->parser);
free(trans->temps);
qir_optimize(c);
if (vc4_debug & VC4_DEBUG_QIR) {
fprintf(stderr, "QIR:\n");
qir_dump(c);
}
vc4_generate_code(c);
if (vc4_debug & VC4_DEBUG_SHADERDB) {
fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
qir_get_stage_name(c->stage), c->qpu_inst_count);
fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
qir_get_stage_name(c->stage), trans->num_uniforms);
}
return trans;
}
static void *
vc4_shader_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
if (!so)
return NULL;
so->tokens = tgsi_dup_tokens(cso->tokens);
return so;
}
static void
copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
int shader_index,
struct tgsi_to_qir *trans)
{
int count = trans->num_uniforms;
struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
uinfo->count = count;
uinfo->data = malloc(count * sizeof(*uinfo->data));
memcpy(uinfo->data, trans->uniform_data,
count * sizeof(*uinfo->data));
uinfo->contents = malloc(count * sizeof(*uinfo->contents));
memcpy(uinfo->contents, trans->uniform_contents,
count * sizeof(*uinfo->contents));
}
static void
vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
struct vc4_fs_key *key)
{
struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
&key->base);
shader->num_inputs = trans->c->num_inputs;
copy_uniform_state_to_shader(shader, 0, trans);
shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
trans->c->qpu_inst_count * sizeof(uint64_t),
"fs_code");
qir_compile_destroy(trans->c);
free(trans);
}
static void
vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
struct vc4_vs_key *key)
{
struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
QSTAGE_VERT,
&key->base);
copy_uniform_state_to_shader(shader, 0, vs_trans);
struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
QSTAGE_COORD,
&key->base);
copy_uniform_state_to_shader(shader, 1, cs_trans);
uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
shader->coord_shader_offset = vs_size; /* XXX: alignment? */
shader->bo = vc4_bo_alloc(vc4->screen,
shader->coord_shader_offset + cs_size,
"vs_code");
void *map = vc4_bo_map(shader->bo);
memcpy(map, vs_trans->c->qpu_insts, vs_size);
memcpy(map + shader->coord_shader_offset,
cs_trans->c->qpu_insts, cs_size);
qir_compile_destroy(vs_trans->c);
qir_compile_destroy(cs_trans->c);
}
static void
vc4_update_compiled_fs(struct vc4_context *vc4)
{
struct vc4_fs_key local_key;
struct vc4_fs_key *key = &local_key;
memset(key, 0, sizeof(*key));
key->base.shader_state = vc4->prog.bind_fs;
if (vc4->framebuffer.cbufs[0])
key->color_format = vc4->framebuffer.cbufs[0]->format;
vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
if (vc4->prog.fs)
return;
key = malloc(sizeof(*key));
memcpy(key, &local_key, sizeof(*key));
struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
vc4_fs_compile(vc4, shader, key);
util_hash_table_set(vc4->fs_cache, key, shader);
vc4->prog.fs = shader;
}
static void
vc4_update_compiled_vs(struct vc4_context *vc4)
{
struct vc4_vs_key local_key;
struct vc4_vs_key *key = &local_key;
memset(key, 0, sizeof(*key));
key->base.shader_state = vc4->prog.bind_vs;
for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
if (vc4->prog.vs)
return;
key = malloc(sizeof(*key));
memcpy(key, &local_key, sizeof(*key));
struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
vc4_vs_compile(vc4, shader, key);
util_hash_table_set(vc4->vs_cache, key, shader);
vc4->prog.vs = shader;
}
void
vc4_update_compiled_shaders(struct vc4_context *vc4)
{
vc4_update_compiled_fs(vc4);
vc4_update_compiled_vs(vc4);
}
static unsigned
fs_cache_hash(void *key)
{
return util_hash_crc32(key, sizeof(struct vc4_fs_key));
}
static unsigned
vs_cache_hash(void *key)
{
return util_hash_crc32(key, sizeof(struct vc4_vs_key));
}
static int
fs_cache_compare(void *key1, void *key2)
{
return memcmp(key1, key2, sizeof(struct vc4_fs_key));
}
static int
vs_cache_compare(void *key1, void *key2)
{
return memcmp(key1, key2, sizeof(struct vc4_vs_key));
}
struct delete_state {
struct vc4_context *vc4;
struct pipe_shader_state *shader_state;
};
static enum pipe_error
fs_delete_from_cache(void *in_key, void *in_value, void *data)
{
struct delete_state *del = data;
struct vc4_fs_key *key = in_key;
struct vc4_compiled_shader *shader = in_value;
if (key->base.shader_state == data) {
util_hash_table_remove(del->vc4->fs_cache, key);
vc4_bo_unreference(&shader->bo);
free(shader);
}
return 0;
}
static enum pipe_error
vs_delete_from_cache(void *in_key, void *in_value, void *data)
{
struct delete_state *del = data;
struct vc4_vs_key *key = in_key;
struct vc4_compiled_shader *shader = in_value;
if (key->base.shader_state == data) {
util_hash_table_remove(del->vc4->vs_cache, key);
vc4_bo_unreference(&shader->bo);
free(shader);
}
return 0;
}
static void
vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
{
struct vc4_context *vc4 = vc4_context(pctx);
struct pipe_shader_state *so = hwcso;
struct delete_state del;
del.vc4 = vc4;
del.shader_state = so;
util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
free((void *)so->tokens);
free(so);
}
static uint32_t translate_wrap(uint32_t p_wrap)
{
switch (p_wrap) {
case PIPE_TEX_WRAP_REPEAT:
return 0;
case PIPE_TEX_WRAP_CLAMP:
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
return 1;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
return 2;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
return 3;
default:
fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
assert(!"not reached");
return 0;
}
}
static uint32_t
get_texture_p0(struct vc4_texture_stateobj *texstate,
uint32_t tex_and_sampler)
{
uint32_t texi = (tex_and_sampler >> 0) & 0xff;
struct pipe_sampler_view *texture = texstate->textures[texi];
struct vc4_resource *rsc = vc4_resource(texture->texture);
return (texture->u.tex.last_level |
#if USE_VC4_SIMULATOR
simpenrose_hw_addr(rsc->bo->map) /* XXX */
#else
0 /* XXX */
#endif
/* XXX: data type */);
}
static uint32_t
get_texture_p1(struct vc4_texture_stateobj *texstate,
uint32_t tex_and_sampler)
{
uint32_t texi = (tex_and_sampler >> 0) & 0xff;
uint32_t sampi = (tex_and_sampler >> 8) & 0xff;
struct pipe_sampler_view *texture = texstate->textures[texi];
struct pipe_sampler_state *sampler = texstate->samplers[sampi];
static const uint32_t mipfilter_map[] = {
[PIPE_TEX_MIPFILTER_NEAREST] = 2,
[PIPE_TEX_MIPFILTER_LINEAR] = 4,
[PIPE_TEX_MIPFILTER_NONE] = 0
};
static const uint32_t imgfilter_map[] = {
[PIPE_TEX_FILTER_NEAREST] = 1,
[PIPE_TEX_FILTER_LINEAR] = 0,
};
return ((1 << 31) /* XXX: data type */|
(texture->texture->height0 << 20) |
(texture->texture->width0 << 8) |
(imgfilter_map[sampler->mag_img_filter] << 7) |
((imgfilter_map[sampler->min_img_filter] +
mipfilter_map[sampler->min_mip_filter]) << 4) |
(translate_wrap(sampler->wrap_t) << 2) |
(translate_wrap(sampler->wrap_s) << 0));
}
static uint32_t
get_texrect_scale(struct vc4_texture_stateobj *texstate,
enum quniform_contents contents,
uint32_t data)
{
struct pipe_sampler_view *texture = texstate->textures[data];
uint32_t dim;
if (contents == QUNIFORM_TEXRECT_SCALE_X)
dim = texture->texture->width0;
else
dim = texture->texture->height0;
return fui(1.0f / dim);
}
void
vc4_get_uniform_bo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
struct vc4_constbuf_stateobj *cb,
struct vc4_texture_stateobj *texstate,
int shader_index, struct vc4_bo **out_bo,
uint32_t *out_offset)
{
struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen,
MAX2(1, uinfo->count * 4), "ubo");
uint32_t *map = vc4_bo_map(ubo);
for (int i = 0; i < uinfo->count; i++) {
switch (uinfo->contents[i]) {
case QUNIFORM_CONSTANT:
map[i] = uinfo->data[i];
break;
case QUNIFORM_UNIFORM:
map[i] = ((uint32_t *)cb->cb[0].user_buffer)[uinfo->data[i]];
break;
case QUNIFORM_VIEWPORT_X_SCALE:
map[i] = fui(vc4->framebuffer.width * 16.0f / 2.0f);
break;
case QUNIFORM_VIEWPORT_Y_SCALE:
map[i] = fui(vc4->framebuffer.height * -16.0f / 2.0f);
break;
case QUNIFORM_TEXTURE_CONFIG_P0:
map[i] = get_texture_p0(texstate, uinfo->data[i]);
break;
case QUNIFORM_TEXTURE_CONFIG_P1:
map[i] = get_texture_p1(texstate, uinfo->data[i]);
break;
case QUNIFORM_TEXRECT_SCALE_X:
case QUNIFORM_TEXRECT_SCALE_Y:
map[i] = get_texrect_scale(texstate,
uinfo->contents[i],
uinfo->data[i]);
break;
}
#if 0
fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
shader, shader_index, i, map[i], uif(map[i]));
#endif
}
*out_bo = ubo;
*out_offset = 0;
}
static void
vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
{
struct vc4_context *vc4 = vc4_context(pctx);
vc4->prog.bind_fs = hwcso;
vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
vc4->dirty |= VC4_DIRTY_PROG;
}
static void
vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
{
struct vc4_context *vc4 = vc4_context(pctx);
vc4->prog.bind_vs = hwcso;
vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
vc4->dirty |= VC4_DIRTY_PROG;
}
void
vc4_program_init(struct pipe_context *pctx)
{
struct vc4_context *vc4 = vc4_context(pctx);
pctx->create_vs_state = vc4_shader_state_create;
pctx->delete_vs_state = vc4_shader_state_delete;
pctx->create_fs_state = vc4_shader_state_create;
pctx->delete_fs_state = vc4_shader_state_delete;
pctx->bind_fs_state = vc4_fp_state_bind;
pctx->bind_vs_state = vc4_vp_state_bind;
vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
}
|