1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
|
//===-- R600LowerShaderInstructions.cpp - TODO: Add brief description -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPULowerShaderInstructions.h"
#include "AMDGPUUtil.h"
#include "AMDIL.h"
#include "AMDILInstrInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
namespace {
class R600LowerShaderInstructionsPass : public MachineFunctionPass,
public AMDGPULowerShaderInstructionsPass {
private:
static char ID;
TargetMachine &TM;
void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);
bool lowerSTORE_OUTPUT(MachineInstr & MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);
public:
R600LowerShaderInstructionsPass(TargetMachine &tm) :
MachineFunctionPass(ID), TM(tm) { }
bool runOnMachineFunction(MachineFunction &MF);
const char *getPassName() const { return "R600 Lower Shader Instructions"; }
};
} /* End anonymous namespace */
char R600LowerShaderInstructionsPass::ID = 0;
FunctionPass *llvm::createR600LowerShaderInstructionsPass(TargetMachine &tm) {
return new R600LowerShaderInstructionsPass(tm);
}
#define INSTR_CASE_FLOAT_V(inst) \
case AMDIL:: inst##_v4f32: \
#define INSTR_CASE_FLOAT_S(inst) \
case AMDIL:: inst##_f32:
#define INSTR_CASE_FLOAT(inst) \
INSTR_CASE_FLOAT_V(inst) \
INSTR_CASE_FLOAT_S(inst)
bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
{
MRI = &MF.getRegInfo();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end();) {
MachineInstr &MI = *I;
bool deleteInstr = false;
switch (MI.getOpcode()) {
default: break;
case AMDIL::RESERVE_REG:
case AMDIL::EXPORT_REG:
deleteInstr = true;
break;
case AMDIL::STORE_OUTPUT:
deleteInstr = lowerSTORE_OUTPUT(MI, MBB, I);
break;
}
++I;
if (deleteInstr) {
MI.eraseFromParent();
}
}
}
return false;
}
bool R600LowerShaderInstructionsPass::lowerSTORE_OUTPUT(MachineInstr &MI,
MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
{
MachineOperand &valueOp = MI.getOperand(1);
MachineOperand &indexOp = MI.getOperand(2);
unsigned valueReg = valueOp.getReg();
int64_t outputIndex = indexOp.getImm();
const TargetRegisterClass * outputClass = TM.getRegisterInfo()->getRegClass(AMDIL::R600_TReg32RegClassID);
unsigned newRegister = outputClass->getRegister(outputIndex);
BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::COPY),
newRegister)
.addReg(valueReg);
if (!MRI->isLiveOut(newRegister))
MRI->addLiveOut(newRegister);
return true;
}
|
