1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
|
//===-- R600LowerInstructions.cpp - Lower unsupported AMDIL instructions --===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This pass lowers AMDIL MachineInstrs that aren't supported by the R600
// target to either supported AMDIL MachineInstrs or R600 MachineInstrs.
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUUtil.h"
#include "AMDIL.h"
#include "AMDILRegisterInfo.h"
#include "R600InstrInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Constants.h"
#include "llvm/Target/TargetInstrInfo.h"
#include <stdio.h>
using namespace llvm;
namespace {
class R600LowerInstructionsPass : public MachineFunctionPass {
private:
static char ID;
TargetMachine &TM;
const R600InstrInfo * TII;
MachineRegisterInfo * MRI;
void lowerFLT(MachineInstr &MI);
void calcAddress(const MachineOperand &ptrOp,
const MachineOperand &indexOp,
unsigned indexReg,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
public:
R600LowerInstructionsPass(TargetMachine &tm) :
MachineFunctionPass(ID), TM(tm),
TII(static_cast<const R600InstrInfo*>(tm.getInstrInfo())),
MRI(NULL)
{ }
const char *getPassName() const { return "R600 Lower Instructions"; }
virtual bool runOnMachineFunction(MachineFunction &MF);
};
} /* End anonymous namespace */
char R600LowerInstructionsPass::ID = 0;
FunctionPass *llvm::createR600LowerInstructionsPass(TargetMachine &tm) {
return new R600LowerInstructionsPass(tm);
}
bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
{
MRI = &MF.getRegInfo();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
I != MBB.end(); I = Next, Next = llvm::next(I) ) {
MachineInstr &MI = *I;
switch(MI.getOpcode()) {
case AMDIL::FLT:
BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::FGE))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(2))
.addOperand(MI.getOperand(1));
break;
/* XXX: Figure out the semantics of DIV_INF_f32 and make sure this is OK */
/* case AMDIL::DIV_INF_f32:
{
unsigned tmp0 = MRI->createVirtualRegister(&AMDIL::GPRF32RegClass);
BuildMI(MBB, I, MBB.findDebugLoc(I),
TM.getInstrInfo()->get(AMDIL::RECIP_CLAMPED), tmp0)
.addOperand(MI.getOperand(2));
BuildMI(MBB, I, MBB.findDebugLoc(I),
TM.getInstrInfo()->get(AMDIL::MUL_IEEE_f32))
.addOperand(MI.getOperand(0))
.addReg(tmp0)
.addOperand(MI.getOperand(1));
break;
}
*/ /* XXX: This is an optimization */
case AMDIL::GLOBALLOAD_f32:
case AMDIL::GLOBALLOAD_i32:
{
MachineOperand &ptrOperand = MI.getOperand(1);
MachineOperand &indexOperand = MI.getOperand(2);
unsigned indexReg =
MRI->createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
/* Calculate the address with in the VTX buffer */
calcAddress(ptrOperand, indexOperand, indexReg, MBB, I);
/* Make sure the VTX_READ_eg writes to the X chan */
MRI->setRegClass(MI.getOperand(0).getReg(),
&AMDIL::R600_TReg32_XRegClass);
/* Add the VTX_READ_eg instruction */
BuildMI(MBB, I, MBB.findDebugLoc(I),
TII->get(AMDIL::VTX_READ_eg))
.addOperand(MI.getOperand(0))
.addReg(indexReg)
.addImm(1);
break;
}
case AMDIL::GLOBALSTORE_i32:
case AMDIL::GLOBALSTORE_f32:
{
MachineOperand &ptrOperand = MI.getOperand(1);
MachineOperand &indexOperand = MI.getOperand(2);
unsigned rwReg =
MRI->createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
unsigned byteIndexReg =
MRI->createVirtualRegister(&AMDIL::R600_TReg32RegClass);
unsigned shiftReg =
MRI->createVirtualRegister(&AMDIL::R600_TReg32RegClass);
unsigned indexReg =
MRI->createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
/* Move the store value to the correct register class */
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::COPY), rwReg)
.addOperand(MI.getOperand(0));
/* Calculate the address in the RAT */
calcAddress(ptrOperand, indexOperand, byteIndexReg, MBB, I);
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::MOV), shiftReg)
.addReg(AMDIL::ALU_LITERAL_X)
.addImm(2);
/* XXX: Check GPU family */
BuildMI(MBB, I, MBB.findDebugLoc(I),
TII->get(AMDIL::LSHR_eg), indexReg)
.addReg(byteIndexReg)
.addReg(shiftReg);
/* XXX: Check GPU Family */
BuildMI(MBB, I, MBB.findDebugLoc(I),
TII->get(AMDIL::RAT_WRITE_CACHELESS_eg))
.addReg(rwReg)
.addReg(indexReg)
.addImm(0);
break;
}
case AMDIL::IL_ASINT_f32:
case AMDIL::IL_ASINT_i32:
case AMDIL::IL_ASFLOAT_f32:
case AMDIL::IL_ASFLOAT_i32:
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::COPY))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(1));
break;
case AMDIL::ILT:
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SETGT_INT))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(2))
.addOperand(MI.getOperand(1));
break;
case AMDIL::LOADCONST_f32:
case AMDIL::LOADCONST_i32:
{
bool canInline = false;
unsigned inlineReg;
MachineOperand & dstOp = MI.getOperand(0);
MachineOperand & immOp = MI.getOperand(1);
if (immOp.isFPImm()) {
const ConstantFP * cfp = immOp.getFPImm();
if (cfp->isZero()) {
canInline = true;
inlineReg = AMDIL::ZERO;
} else if (cfp->isExactlyValue(1.0f)) {
canInline = true;
inlineReg = AMDIL::ONE;
} else if (cfp->isExactlyValue(0.5f)) {
canInline = true;
inlineReg = AMDIL::HALF;
}
}
if (canInline) {
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::COPY))
.addOperand(dstOp)
.addReg(inlineReg);
} else {
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::MOV))
.addOperand(dstOp)
.addReg(AMDIL::ALU_LITERAL_X)
.addOperand(immOp);
}
break;
}
case AMDIL::MASK_WRITE:
{
unsigned maskedRegister = MI.getOperand(0).getReg();
assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
MachineInstr * defInstr = MRI->getVRegDef(maskedRegister);
MachineOperand * def = defInstr->findRegisterDefOperand(maskedRegister);
def->addTargetFlag(MO_FLAG_MASK);
/* Continue so the instruction is not erased */
continue;
}
case AMDIL::ULT:
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SETGT_UINT))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(2))
.addOperand(MI.getOperand(1));
break;
default:
continue;
}
MI.eraseFromParent();
}
}
return false;
}
void R600LowerInstructionsPass::calcAddress(const MachineOperand &ptrOp,
const MachineOperand &indexOp,
unsigned indexReg,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const
{
/* Optimize the case where the indexOperand is 0 */
if (indexOp.isImm() && indexOp.getImm() == 0) {
assert(ptrOp.isReg());
BuildMI(MBB, I, MBB.findDebugLoc(I),
TII->get(AMDIL::COPY), indexReg)
.addOperand(ptrOp);
} else {
BuildMI(MBB, I, MBB.findDebugLoc(I),
TII->get(AMDIL::ADD_INT), indexReg)
.addOperand(indexOp)
.addOperand(ptrOp);
}
}
|
