blob: 6dc62320f406017a0ec35dab759080e7dd9c3c11 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
GENERATED_SOURCES := \
R600Intrinsics.td \
R600RegisterInfo.td \
AMDGPUInstrEnums.td \
SIRegisterInfo.td \
SIRegisterGetHWRegNum.inc \
AMDILGenRegisterInfo.inc \
AMDILGenInstrInfo.inc \
AMDILGenAsmWriter.inc \
AMDILGenDAGISel.inc \
AMDILGenCallingConv.inc \
AMDILGenSubtargetInfo.inc \
AMDILGenEDInfo.inc \
AMDILGenIntrinsics.inc \
AMDILGenCodeEmitter.inc \
AMDGPUInstrEnums.h.include \
AMDGPUInstrEnums.include
CPP_SOURCES := \
AMDIL7XXDevice.cpp \
AMDILCFGStructurizer.cpp \
AMDILDevice.cpp \
AMDILDeviceInfo.cpp \
AMDILEvergreenDevice.cpp \
AMDILFrameLowering.cpp \
AMDILInstrInfo.cpp \
AMDILIntrinsicInfo.cpp \
AMDILISelDAGToDAG.cpp \
AMDILISelLowering.cpp \
AMDILMachinePeephole.cpp \
AMDILNIDevice.cpp \
AMDILPeepholeOptimizer.cpp \
AMDILRegisterInfo.cpp \
AMDILSIDevice.cpp \
AMDILSubtarget.cpp \
AMDILTargetMachine.cpp \
AMDGPUTargetMachine.cpp \
AMDGPUISelLowering.cpp \
AMDGPUConvertToISA.cpp \
AMDGPULowerInstructions.cpp \
AMDGPUInstrInfo.cpp \
AMDGPURegisterInfo.cpp \
AMDGPUUtil.cpp \
R600CodeEmitter.cpp \
R600ISelLowering.cpp \
R600InstrInfo.cpp \
R600KernelParameters.cpp \
R600LowerInstructions.cpp \
R600MachineFunctionInfo.cpp \
R600RegisterInfo.cpp \
SIAssignInterpRegs.cpp \
SICodeEmitter.cpp \
SIInstrInfo.cpp \
SIISelLowering.cpp \
SIMachineFunctionInfo.cpp \
SIPropagateImmReads.cpp \
SIRegisterInfo.cpp \
MCTargetDesc/AMDILMCAsmInfo.cpp \
MCTargetDesc/AMDILMCTargetDesc.cpp \
TargetInfo/AMDILTargetInfo.cpp \
radeon_llvm_emit.cpp
C_SOURCES := \
radeon_setup_tgsi_llvm.c
|
