blob: 5e793422d66ece00124bab550b1ce6222e72862c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
|
TD_FILES := \
AMDGPU.td \
AMDGPUInstrInfo.td \
AMDGPUInstructions.td \
AMDGPUIntrinsics.td \
AMDGPURegisterInfo.td \
AMDILBase.td \
AMDILInstrInfo.td \
AMDILIntrinsics.td \
AMDILRegisterInfo.td \
Processors.td \
R600Instructions.td \
R600Intrinsics.td \
R600IntrinsicsNoOpenCL.td \
R600IntrinsicsOpenCL.td \
R600RegisterInfo.td \
R600Schedule.td \
SIInstrFormats.td \
SIInstrInfo.td \
SIInstructions.td \
SIIntrinsics.td \
SIRegisterInfo.td \
SISchedule.td
LLVM_GENERATED_SOURCES := \
R600Intrinsics.td \
R600RegisterInfo.td \
SIRegisterInfo.td \
SIRegisterGetHWRegNum.inc \
AMDGPUGenRegisterInfo.inc \
AMDGPUGenInstrInfo.inc \
AMDGPUGenAsmWriter.inc \
AMDGPUGenDAGISel.inc \
AMDGPUGenCallingConv.inc \
AMDGPUGenSubtargetInfo.inc \
AMDGPUGenEDInfo.inc \
AMDGPUGenIntrinsics.inc \
AMDGPUGenCodeEmitter.inc \
AMDGPUGenMCCodeEmitter.inc \
AMDGPUGenDFAPacketizer.inc
LLVM_CPP_SOURCES := \
AMDIL7XXDevice.cpp \
AMDILCFGStructurizer.cpp \
AMDILDevice.cpp \
AMDILDeviceInfo.cpp \
AMDILEvergreenDevice.cpp \
AMDILFrameLowering.cpp \
AMDILIntrinsicInfo.cpp \
AMDILISelDAGToDAG.cpp \
AMDILISelLowering.cpp \
AMDILNIDevice.cpp \
AMDILPeepholeOptimizer.cpp \
AMDILSIDevice.cpp \
AMDGPUAsmPrinter.cpp \
AMDGPUMCInstLower.cpp \
AMDGPUSubtarget.cpp \
AMDGPUTargetMachine.cpp \
AMDGPUISelLowering.cpp \
AMDGPUConvertToISA.cpp \
AMDGPUInstrInfo.cpp \
AMDGPURegisterInfo.cpp \
R600ExpandSpecialInstrs.cpp \
R600ISelLowering.cpp \
R600InstrInfo.cpp \
R600MachineFunctionInfo.cpp \
R600RegisterInfo.cpp \
SIAssignInterpRegs.cpp \
SIInstrInfo.cpp \
SIISelLowering.cpp \
SILowerLiteralConstants.cpp \
SILowerFlowControl.cpp \
SIMachineFunctionInfo.cpp \
SIRegisterInfo.cpp \
InstPrinter/AMDGPUInstPrinter.cpp \
MCTargetDesc/AMDGPUMCAsmInfo.cpp \
MCTargetDesc/AMDGPUAsmBackend.cpp \
MCTargetDesc/AMDGPUMCTargetDesc.cpp \
MCTargetDesc/SIMCCodeEmitter.cpp \
MCTargetDesc/R600MCCodeEmitter.cpp \
TargetInfo/AMDGPUTargetInfo.cpp \
CPP_SOURCES := \
radeon_llvm_emit.cpp
C_SOURCES := \
radeon_setup_tgsi_llvm.c
|
