blob: 989ccd9faf740d6cb2c612b4bd2f42be68cdc68b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
|
//===- AMDILRegisterInfo.cpp - AMDIL Register Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//==-----------------------------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AMDIL implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "AMDILRegisterInfo.h"
#include "AMDIL.h"
#include "AMDILInstrInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
AMDILRegisterInfo::AMDILRegisterInfo(TargetMachine &tm,
const TargetInstrInfo &tii)
: AMDILGenRegisterInfo(0), // RA???
TM(tm), TII(tii)
{
baseOffset = 0;
nextFuncOffset = 0;
}
const uint16_t*
AMDILRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
{
static const uint16_t CalleeSavedRegs[] = { 0 };
// TODO: Does IL need to actually have any callee saved regs?
// I don't think we do since we can just use sequential registers
// Maybe this would be easier if every function call was inlined first
// and then there would be no callee issues to deal with
//TODO(getCalleeSavedRegs);
return CalleeSavedRegs;
}
BitVector
AMDILRegisterInfo::getReservedRegs(const MachineFunction &MF) const
{
BitVector Reserved(getNumRegs());
// We reserve the first getNumRegs() registers as they are the ones passed
// in live-in/live-out
// and therefor cannot be killed by the scheduler. This works around a bug
// discovered
// that was causing the linearscan register allocator to kill registers
// inside of the
// function that were also passed as LiveIn registers.
for (unsigned int x = 0, y = 256; x < y; ++x) {
Reserved.set(x);
}
return Reserved;
}
BitVector
AMDILRegisterInfo::getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC = NULL) const
{
BitVector Allocatable(getNumRegs());
Allocatable.clear();
return Allocatable;
}
const TargetRegisterClass* const*
AMDILRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
{
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
// TODO: Keep in sync with getCalleeSavedRegs
//TODO(getCalleeSavedRegClasses);
return CalleeSavedRegClasses;
}
void
AMDILRegisterInfo::eliminateCallFramePseudoInstr(
MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const
{
MBB.erase(I);
}
// For each frame index we find, we store the offset in the stack which is
// being pushed back into the global buffer. The offset into the stack where
// the value is stored is copied into a new register and the frame index is
// then replaced with that register.
void
AMDILRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj,
RegScavenger *RS) const
{
assert(!"Implement");
}
void
AMDILRegisterInfo::processFunctionBeforeFrameFinalized(
MachineFunction &MF) const
{
//TODO(processFunctionBeforeFrameFinalized);
// Here we keep track of the amount of stack that the current function
// uses so
// that we can set the offset to the end of the stack and any other
// function call
// will not overwrite any stack variables.
// baseOffset = nextFuncOffset;
MachineFrameInfo *MFI = MF.getFrameInfo();
for (uint32_t x = 0, y = MFI->getNumObjects(); x < y; ++x) {
int64_t size = MFI->getObjectSize(x);
if (!(size % 4) && size > 1) {
nextFuncOffset += size;
} else {
nextFuncOffset += 16;
}
}
}
unsigned int
AMDILRegisterInfo::getRARegister() const
{
return AMDGPU::RA;
}
unsigned int
AMDILRegisterInfo::getFrameRegister(const MachineFunction &MF) const
{
return AMDGPU::FP;
}
unsigned int
AMDILRegisterInfo::getEHExceptionRegister() const
{
assert(0 && "What is the exception register");
return 0;
}
unsigned int
AMDILRegisterInfo::getEHHandlerRegister() const
{
assert(0 && "What is the exception handler register");
return 0;
}
int64_t
AMDILRegisterInfo::getStackSize() const
{
return nextFuncOffset - baseOffset;
}
#define GET_REGINFO_TARGET_DESC
#include "AMDGPUGenRegisterInfo.inc"
|
