blob: b0d4e8a519c3350fafb5c74c753eac2845386b79 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the definition of a TargetInstrInfo class that is common
// to all AMD GPUs.
//
//===----------------------------------------------------------------------===//
#ifndef AMDGPUINSTRUCTIONINFO_H_
#define AMDGPUINSTRUCTIONINFO_H_
#include "AMDGPURegisterInfo.h"
#include "AMDILInstrInfo.h"
#include <map>
namespace llvm {
class AMDGPUTargetMachine;
class MachineFunction;
class MachineInstr;
class MachineInstrBuilder;
class AMDGPUInstrInfo : public AMDILInstrInfo {
private:
AMDGPUTargetMachine & TM;
public:
explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm);
virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
/// getISAOpcode - This function takes an AMDIL opcode as an argument and
/// returns an equivalent ISA opcode.
virtual unsigned getISAOpcode(unsigned AMDILopcode) const = 0;
/// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
/// MachineInstr
virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const;
};
} // End llvm namespace
#endif // AMDGPUINSTRINFO_H_
|
