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/* $Id: enums.c,v 1.4 1999/11/08 07:36:44 brianp Exp $ */

/*
 * Mesa 3-D graphics library
 * Version:  3.1
 * 
 * Copyright (C) 1999  Brian Paul   All Rights Reserved.
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef XFree86Server
#include <stdlib.h>
#include <string.h>
#else
#include "GL/xf86glx.h"
#endif

#include "GL/gl.h"
#include "enums.h"
#include "macros.h"


typedef struct { 
   const char *c; 
   int n; 
} enum_elt;

enum_elt all_enums[] = 
{
   /* Boolean values */
   { "GL_FALSE", 0 },
   { "GL_TRUE", 1 },

   /* Data types */
   { "GL_BYTE", 0x1400 },
   { "GL_UNSIGNED_BYTE", 0x1401 },
   { "GL_SHORT", 0x1402 },
   { "GL_UNSIGNED_SHORT", 0x1403 },
   { "GL_INT", 0x1404 },
   { "GL_UNSIGNED_INT", 0x1405 },
   { "GL_FLOAT", 0x1406 },
   { "GL_DOUBLE", 0x140A },
   { "GL_2_BYTES", 0x1407 },
   { "GL_3_BYTES", 0x1408 },
   { "GL_4_BYTES", 0x1409 },

   /* Primitives */
   { "GL_LINES", 0x0001 },
   { "GL_POINTS", 0x0000 },
   { "GL_LINE_STRIP", 0x0003 },
   { "GL_LINE_LOOP", 0x0002 },
   { "GL_TRIANGLES", 0x0004 },
   { "GL_TRIANGLE_STRIP", 0x0005 },
   { "GL_TRIANGLE_FAN", 0x0006 },
   { "GL_QUADS", 0x0007 },
   { "GL_QUAD_STRIP", 0x0008 },
   { "GL_POLYGON", 0x0009 },
   { "GL_EDGE_FLAG", 0x0B43 },

   /* Vertex Arrays */
   { "GL_VERTEX_ARRAY", 0x8074 },
   { "GL_NORMAL_ARRAY", 0x8075 },
   { "GL_COLOR_ARRAY", 0x8076 },
   { "GL_INDEX_ARRAY", 0x8077 },
   { "GL_TEXTURE_COORD_ARRAY", 0x8078 },
   { "GL_EDGE_FLAG_ARRAY", 0x8079 },
   { "GL_VERTEX_ARRAY_SIZE", 0x807A },
   { "GL_VERTEX_ARRAY_TYPE", 0x807B },
   { "GL_VERTEX_ARRAY_STRIDE", 0x807C },
   { "GL_NORMAL_ARRAY_TYPE", 0x807E },
   { "GL_NORMAL_ARRAY_STRIDE", 0x807F },
   { "GL_COLOR_ARRAY_SIZE", 0x8081 },
   { "GL_COLOR_ARRAY_TYPE", 0x8082 },
   { "GL_COLOR_ARRAY_STRIDE", 0x8083 },
   { "GL_INDEX_ARRAY_TYPE", 0x8085 },
   { "GL_INDEX_ARRAY_STRIDE", 0x8086 },
   { "GL_TEXTURE_COORD_ARRAY_SIZE", 0x8088 },
   { "GL_TEXTURE_COORD_ARRAY_TYPE", 0x8089 },
   { "GL_TEXTURE_COORD_ARRAY_STRIDE", 0x808A },
   { "GL_EDGE_FLAG_ARRAY_STRIDE", 0x808C },
   { "GL_VERTEX_ARRAY_POINTER", 0x808E },
   { "GL_NORMAL_ARRAY_POINTER", 0x808F },
   { "GL_COLOR_ARRAY_POINTER", 0x8090 },
   { "GL_INDEX_ARRAY_POINTER", 0x8091 },
   { "GL_TEXTURE_COORD_ARRAY_POINTER", 0x8092 },
   { "GL_EDGE_FLAG_ARRAY_POINTER", 0x8093 },
   { "GL_V2F", 0x2A20 },
   { "GL_V3F", 0x2A21 },
   { "GL_C4UB_V2F", 0x2A22 },
   { "GL_C4UB_V3F", 0x2A23 },
   { "GL_C3F_V3F", 0x2A24 },
   { "GL_N3F_V3F", 0x2A25 },
   { "GL_C4F_N3F_V3F", 0x2A26 },
   { "GL_T2F_V3F", 0x2A27 },
   { "GL_T4F_V4F", 0x2A28 },
   { "GL_T2F_C4UB_V3F", 0x2A29 },
   { "GL_T2F_C3F_V3F", 0x2A2A },
   { "GL_T2F_N3F_V3F", 0x2A2B },
   { "GL_T2F_C4F_N3F_V3F", 0x2A2C },
   { "GL_T4F_C4F_N3F_V4F", 0x2A2D },

   /* Matrix Mode */
   { "GL_MATRIX_MODE", 0x0BA0 },
   { "GL_MODELVIEW", 0x1700 },
   { "GL_PROJECTION", 0x1701 },
   { "GL_TEXTURE", 0x1702 },

   /* Points */
   { "GL_POINT_SMOOTH", 0x0B10 },
   { "GL_POINT_SIZE", 0x0B11 },
   { "GL_POINT_SIZE_GRANULARITY ", 0x0B13 },
   { "GL_POINT_SIZE_RANGE", 0x0B12 },

   /* Lines */
   { "GL_LINE_SMOOTH", 0x0B20 },
   { "GL_LINE_STIPPLE", 0x0B24 },
   { "GL_LINE_STIPPLE_PATTERN", 0x0B25 },
   { "GL_LINE_STIPPLE_REPEAT", 0x0B26 },
   { "GL_LINE_WIDTH", 0x0B21 },
   { "GL_LINE_WIDTH_GRANULARITY", 0x0B23 },
   { "GL_LINE_WIDTH_RANGE", 0x0B22 },

   /* Polygons */
   { "GL_POINT", 0x1B00 },
   { "GL_LINE", 0x1B01 },
   { "GL_FILL", 0x1B02 },
   { "GL_CCW", 0x0901 },
   { "GL_CW", 0x0900 },
   { "GL_FRONT", 0x0404 },
   { "GL_BACK", 0x0405 },
   { "GL_CULL_FACE", 0x0B44 },
   { "GL_CULL_FACE_MODE", 0x0B45 },
   { "GL_POLYGON_SMOOTH", 0x0B41 },
   { "GL_POLYGON_STIPPLE", 0x0B42 },
   { "GL_FRONT_FACE", 0x0B46 },
   { "GL_POLYGON_MODE", 0x0B40 },
   { "GL_POLYGON_OFFSET_FACTOR", 0x8038 },
   { "GL_POLYGON_OFFSET_UNITS", 0x2A00 },
   { "GL_POLYGON_OFFSET_POINT", 0x2A01 },
   { "GL_POLYGON_OFFSET_LINE", 0x2A02 },
   { "GL_POLYGON_OFFSET_FILL", 0x8037 },

   /* Display Lists */
   { "GL_COMPILE", 0x1300 },
   { "GL_COMPILE_AND_EXECUTE", 0x1301 },
   { "GL_LIST_BASE", 0x0B32 },
   { "GL_LIST_INDEX", 0x0B33 },
   { "GL_LIST_MODE", 0x0B30 },

   /* Depth buffer */
   { "GL_NEVER", 0x0200 },
   { "GL_LESS", 0x0201 },
   { "GL_GEQUAL", 0x0206 },
   { "GL_LEQUAL", 0x0203 },
   { "GL_GREATER", 0x0204 },
   { "GL_NOTEQUAL", 0x0205 },
   { "GL_EQUAL", 0x0202 },
   { "GL_ALWAYS", 0x0207 },
   { "GL_DEPTH_TEST", 0x0B71 },
   { "GL_DEPTH_BITS", 0x0D56 },
   { "GL_DEPTH_CLEAR_VALUE", 0x0B73 },
   { "GL_DEPTH_FUNC", 0x0B74 },
   { "GL_DEPTH_RANGE", 0x0B70 },
   { "GL_DEPTH_WRITEMASK", 0x0B72 },
   { "GL_DEPTH_COMPONENT", 0x1902 },

   /* Lighting */
   { "GL_LIGHTING", 0x0B50 },
   { "GL_LIGHT0", 0x4000 },
   { "GL_LIGHT1", 0x4001 },
   { "GL_LIGHT2", 0x4002 },
   { "GL_LIGHT3", 0x4003 },
   { "GL_LIGHT4", 0x4004 },
   { "GL_LIGHT5", 0x4005 },
   { "GL_LIGHT6", 0x4006 },
   { "GL_LIGHT7", 0x4007 },
   { "GL_SPOT_EXPONENT", 0x1205 },
   { "GL_SPOT_CUTOFF", 0x1206 },
   { "GL_CONSTANT_ATTENUATION", 0x1207 },
   { "GL_LINEAR_ATTENUATION", 0x1208 },
   { "GL_QUADRATIC_ATTENUATION", 0x1209 },
   { "GL_AMBIENT", 0x1200 },
   { "GL_DIFFUSE", 0x1201 },
   { "GL_SPECULAR", 0x1202 },
   { "GL_SHININESS", 0x1601 },
   { "GL_EMISSION", 0x1600 },
   { "GL_POSITION", 0x1203 },
   { "GL_SPOT_DIRECTION", 0x1204 },
   { "GL_AMBIENT_AND_DIFFUSE", 0x1602 },
   { "GL_COLOR_INDEXES", 0x1603 },
   { "GL_LIGHT_MODEL_TWO_SIDE", 0x0B52 },
   { "GL_LIGHT_MODEL_LOCAL_VIEWER", 0x0B51 },
   { "GL_LIGHT_MODEL_AMBIENT", 0x0B53 },
   { "GL_FRONT_AND_BACK", 0x0408 },
   { "GL_SHADE_MODEL", 0x0B54 },
   { "GL_FLAT", 0x1D00 },
   { "GL_SMOOTH", 0x1D01 },
   { "GL_COLOR_MATERIAL", 0x0B57 },
   { "GL_COLOR_MATERIAL_FACE", 0x0B55 },
   { "GL_COLOR_MATERIAL_PARAMETER", 0x0B56 },
   { "GL_NORMALIZE", 0x0BA1 },

   /* User clipping planes */
   { "GL_CLIP_PLANE0", 0x3000 },
   { "GL_CLIP_PLANE1", 0x3001 },
   { "GL_CLIP_PLANE2", 0x3002 },
   { "GL_CLIP_PLANE3", 0x3003 },
   { "GL_CLIP_PLANE4", 0x3004 },
   { "GL_CLIP_PLANE5", 0x3005 },

   /* Accumulation buffer */
   { "GL_ACCUM_RED_BITS", 0x0D58 },
   { "GL_ACCUM_GREEN_BITS", 0x0D59 },
   { "GL_ACCUM_BLUE_BITS", 0x0D5A },
   { "GL_ACCUM_ALPHA_BITS", 0x0D5B },
   { "GL_ACCUM_CLEAR_VALUE", 0x0B80 },
   { "GL_ACCUM", 0x0100 },
   { "GL_ADD", 0x0104 },
   { "GL_LOAD", 0x0101 },
   { "GL_MULT", 0x0103 },
   { "GL_RETURN", 0x0102 },

   /* Alpha testing */
   { "GL_ALPHA_TEST", 0x0BC0 },
   { "GL_ALPHA_TEST_REF", 0x0BC2 },
   { "GL_ALPHA_TEST_FUNC", 0x0BC1 },

   /* Blending */
   { "GL_BLEND", 0x0BE2 },
   { "GL_BLEND_SRC", 0x0BE1 },
   { "GL_BLEND_DST", 0x0BE0 },
   { "GL_ZERO", 0 },
   { "GL_ONE", 1 },
   { "GL_SRC_COLOR", 0x0300 },
   { "GL_ONE_MINUS_SRC_COLOR", 0x0301 },
   { "GL_DST_COLOR", 0x0306 },
   { "GL_ONE_MINUS_DST_COLOR", 0x0307 },
   { "GL_SRC_ALPHA", 0x0302 },
   { "GL_ONE_MINUS_SRC_ALPHA", 0x0303 },
   { "GL_DST_ALPHA", 0x0304 },
   { "GL_ONE_MINUS_DST_ALPHA", 0x0305 },
   { "GL_SRC_ALPHA_SATURATE", 0x0308 },
   { "GL_CONSTANT_COLOR", 0x8001 },
   { "GL_ONE_MINUS_CONSTANT_COLOR", 0x8002 },
   { "GL_CONSTANT_ALPHA", 0x8003 },
   { "GL_ONE_MINUS_CONSTANT_ALPHA", 0x8004 },

   /* Render Mode */
   { "GL_FEEDBACK", 0x1C01 },
   { "GL_RENDER", 0x1C00 },
   { "GL_SELECT", 0x1C02 },

   /* Feedback */
   { "GL_2D", 0x0600 },
   { "GL_3D", 0x0601 },
   { "GL_3D_COLOR", 0x0602 },
   { "GL_3D_COLOR_TEXTURE", 0x0603 },
   { "GL_4D_COLOR_TEXTURE", 0x0604 },
   { "GL_POINT_TOKEN", 0x0701 },
   { "GL_LINE_TOKEN", 0x0702 },
   { "GL_LINE_RESET_TOKEN", 0x0707 },
   { "GL_POLYGON_TOKEN", 0x0703 },
   { "GL_BITMAP_TOKEN", 0x0704 },
   { "GL_DRAW_PIXEL_TOKEN", 0x0705 },
   { "GL_COPY_PIXEL_TOKEN", 0x0706 },
   { "GL_PASS_THROUGH_TOKEN", 0x0700 },
   { "GL_FEEDBACK_BUFFER_POINTER", 0x0DF0 },
   { "GL_FEEDBACK_BUFFER_SIZE", 0x0DF1 },
   { "GL_FEEDBACK_BUFFER_TYPE", 0x0DF2 },

   /* Selection */
   { "GL_SELECTION_BUFFER_POINTER", 0x0DF3 },
   { "GL_SELECTION_BUFFER_SIZE", 0x0DF4 },

   /* Fog */
   { "GL_FOG", 0x0B60 },
   { "GL_FOG_MODE", 0x0B65 },
   { "GL_FOG_DENSITY", 0x0B62 },
   { "GL_FOG_COLOR", 0x0B66 },
   { "GL_FOG_INDEX", 0x0B61 },
   { "GL_FOG_START", 0x0B63 },
   { "GL_FOG_END", 0x0B64 },
   { "GL_LINEAR", 0x2601 },
   { "GL_EXP", 0x0800 },
   { "GL_EXP2", 0x0801 },

   /* Logic Ops */
   { "GL_LOGIC_OP", 0x0BF1 },
   { "GL_INDEX_LOGIC_OP", 0x0BF1 },
   { "GL_COLOR_LOGIC_OP", 0x0BF2 },
   { "GL_LOGIC_OP_MODE", 0x0BF0 },
   { "GL_CLEAR", 0x1500 },
   { "GL_SET", 0x150F },
   { "GL_COPY", 0x1503 },
   { "GL_COPY_INVERTED", 0x150C },
   { "GL_NOOP", 0x1505 },
   { "GL_INVERT", 0x150A },
   { "GL_AND", 0x1501 },
   { "GL_NAND", 0x150E },
   { "GL_OR", 0x1507 },
   { "GL_NOR", 0x1508 },
   { "GL_XOR", 0x1506 },
   { "GL_EQUIV", 0x1509 },
   { "GL_AND_REVERSE", 0x1502 },
   { "GL_AND_INVERTED", 0x1504 },
   { "GL_OR_REVERSE", 0x150B },
   { "GL_OR_INVERTED", 0x150D },

   /* Stencil */
   { "GL_STENCIL_TEST", 0x0B90 },
   { "GL_STENCIL_WRITEMASK", 0x0B98 },
   { "GL_STENCIL_BITS", 0x0D57 },
   { "GL_STENCIL_FUNC", 0x0B92 },
   { "GL_STENCIL_VALUE_MASK", 0x0B93 },
   { "GL_STENCIL_REF", 0x0B97 },
   { "GL_STENCIL_FAIL", 0x0B94 },
   { "GL_STENCIL_PASS_DEPTH_PASS", 0x0B96 },
   { "GL_STENCIL_PASS_DEPTH_FAIL", 0x0B95 },
   { "GL_STENCIL_CLEAR_VALUE", 0x0B91 },
   { "GL_STENCIL_INDEX", 0x1901 },
   { "GL_KEEP", 0x1E00 },
   { "GL_REPLACE", 0x1E01 },
   { "GL_INCR", 0x1E02 },
   { "GL_DECR", 0x1E03 },

   /* Buffers, Pixel Drawing/Reading */
   { "GL_NONE", 0 },
   { "GL_LEFT", 0x0406 },
   { "GL_RIGHT", 0x0407 },
   { "GL_FRONT_LEFT", 0x0400 },
   { "GL_FRONT_RIGHT", 0x0401 },
   { "GL_BACK_LEFT", 0x0402 },
   { "GL_BACK_RIGHT", 0x0403 },
   { "GL_AUX0", 0x0409 },
   { "GL_AUX1", 0x040A },
   { "GL_AUX2", 0x040B },
   { "GL_AUX3", 0x040C },
   { "GL_COLOR_INDEX", 0x1900 },
   { "GL_RED", 0x1903 },
   { "GL_GREEN", 0x1904 },
   { "GL_BLUE", 0x1905 },
   { "GL_ALPHA", 0x1906 },
   { "GL_LUMINANCE", 0x1909 },
   { "GL_LUMINANCE_ALPHA", 0x190A },
   { "GL_ALPHA_BITS", 0x0D55 },
   { "GL_RED_BITS", 0x0D52 },
   { "GL_GREEN_BITS", 0x0D53 },
   { "GL_BLUE_BITS", 0x0D54 },
   { "GL_INDEX_BITS", 0x0D51 },
   { "GL_SUBPIXEL_BITS", 0x0D50 },
   { "GL_AUX_BUFFERS", 0x0C00 },
   { "GL_READ_BUFFER", 0x0C02 },
   { "GL_DRAW_BUFFER", 0x0C01 },
   { "GL_DOUBLEBUFFER", 0x0C32 },
   { "GL_STEREO", 0x0C33 },
   { "GL_BITMAP", 0x1A00 },
   { "GL_COLOR", 0x1800 },
   { "GL_DEPTH", 0x1801 },
   { "GL_STENCIL", 0x1802 },
   { "GL_DITHER", 0x0BD0 },
   { "GL_RGB", 0x1907 },
   { "GL_RGBA", 0x1908 },

   /* Implementation limits */
   { "GL_MAX_LIST_NESTING", 0x0B31 },
   { "GL_MAX_ATTRIB_STACK_DEPTH", 0x0D35 },
   { "GL_MAX_MODELVIEW_STACK_DEPTH", 0x0D36 },
   { "GL_MAX_NAME_STACK_DEPTH", 0x0D37 },
   { "GL_MAX_PROJECTION_STACK_DEPTH", 0x0D38 },
   { "GL_MAX_TEXTURE_STACK_DEPTH", 0x0D39 },
   { "GL_MAX_EVAL_ORDER", 0x0D30 },
   { "GL_MAX_LIGHTS", 0x0D31 },
   { "GL_MAX_CLIP_PLANES", 0x0D32 },
   { "GL_MAX_TEXTURE_SIZE", 0x0D33 },
   { "GL_MAX_PIXEL_MAP_TABLE", 0x0D34 },
   { "GL_MAX_VIEWPORT_DIMS", 0x0D3A },
   { "GL_MAX_CLIENT_ATTRIB_STACK_DEPTH", 0x0D3B },


   { "GL_ATTRIB_STACK_DEPTH", 0x0BB0 },
   { "GL_CLIENT_ATTRIB_STACK_DEPTH", 0x0BB1 },
   { "GL_COLOR_CLEAR_VALUE", 0x0C22 },
   { "GL_COLOR_WRITEMASK", 0x0C23 },
   { "GL_CURRENT_INDEX", 0x0B01 },
   { "GL_CURRENT_COLOR", 0x0B00 },
   { "GL_CURRENT_NORMAL", 0x0B02 },
   { "GL_CURRENT_RASTER_COLOR", 0x0B04 },
   { "GL_CURRENT_RASTER_DISTANCE", 0x0B09 },
   { "GL_CURRENT_RASTER_INDEX", 0x0B05 },
   { "GL_CURRENT_RASTER_POSITION", 0x0B07 },
   { "GL_CURRENT_RASTER_TEXTURE_COORDS", 0x0B06},
   { "GL_CURRENT_RASTER_POSITION_VALID", 0x0B08 },
   { "GL_CURRENT_TEXTURE_COORDS", 0x0B03 },
   { "GL_INDEX_CLEAR_VALUE", 0x0C20 },
   { "GL_INDEX_MODE", 0x0C30 },
   { "GL_INDEX_WRITEMASK", 0x0C21 },
   { "GL_MODELVIEW_MATRIX", 0x0BA6 },
   { "GL_MODELVIEW_STACK_DEPTH", 0x0BA3 },
   { "GL_NAME_STACK_DEPTH", 0x0D70 },
   { "GL_PROJECTION_MATRIX", 0x0BA7 },
   { "GL_PROJECTION_STACK_DEPTH", 0x0BA4 },
   { "GL_RENDER_MODE", 0x0C40 },
   { "GL_RGBA_MODE", 0x0C31 },
   { "GL_TEXTURE_MATRIX", 0x0BA8 },
   { "GL_TEXTURE_STACK_DEPTH", 0x0BA5 },
   { "GL_VIEWPORT", 0x0BA2 },


   /* Evaluators */
   { "GL_AUTO_NORMAL", 0x0D80 },
   { "GL_MAP1_COLOR_4", 0x0D90 },
   { "GL_MAP1_GRID_DOMAIN", 0x0DD0 },
   { "GL_MAP1_GRID_SEGMENTS", 0x0DD1 },
   { "GL_MAP1_INDEX", 0x0D91 },
   { "GL_MAP1_NORMAL", 0x0D92 },
   { "GL_MAP1_TEXTURE_COORD_1", 0x0D93 },
   { "GL_MAP1_TEXTURE_COORD_2", 0x0D94 },
   { "GL_MAP1_TEXTURE_COORD_3", 0x0D95 },
   { "GL_MAP1_TEXTURE_COORD_4", 0x0D96 },
   { "GL_MAP1_VERTEX_3", 0x0D97 },
   { "GL_MAP1_VERTEX_4", 0x0D98 },
   { "GL_MAP2_COLOR_4", 0x0DB0 },
   { "GL_MAP2_GRID_DOMAIN", 0x0DD2 },
   { "GL_MAP2_GRID_SEGMENTS", 0x0DD3 },
   { "GL_MAP2_INDEX", 0x0DB1 },
   { "GL_MAP2_NORMAL", 0x0DB2 },
   { "GL_MAP2_TEXTURE_COORD_1", 0x0DB3 },
   { "GL_MAP2_TEXTURE_COORD_2", 0x0DB4 },
   { "GL_MAP2_TEXTURE_COORD_3", 0x0DB5 },
   { "GL_MAP2_TEXTURE_COORD_4", 0x0DB6 },
   { "GL_MAP2_VERTEX_3", 0x0DB7 },
   { "GL_MAP2_VERTEX_4", 0x0DB8 },
   { "GL_COEFF", 0x0A00 },
   { "GL_DOMAIN", 0x0A02 },
   { "GL_ORDER", 0x0A01 },

   /* Hints */
   { "GL_FOG_HINT", 0x0C54 },
   { "GL_LINE_SMOOTH_HINT", 0x0C52 },
   { "GL_PERSPECTIVE_CORRECTION_HINT", 0x0C50 },
   { "GL_POINT_SMOOTH_HINT", 0x0C51 },
   { "GL_POLYGON_SMOOTH_HINT", 0x0C53 },
   { "GL_DONT_CARE", 0x1100 },
   { "GL_FASTEST", 0x1101 },
   { "GL_NICEST", 0x1102 },

   /* Scissor box */
   { "GL_SCISSOR_TEST", 0x0C11 },
   { "GL_SCISSOR_BOX", 0x0C10 },

   /* Pixel Mode / Transfer */
   { "GL_MAP_COLOR", 0x0D10 },
   { "GL_MAP_STENCIL", 0x0D11 },
   { "GL_INDEX_SHIFT", 0x0D12 },
   { "GL_INDEX_OFFSET", 0x0D13 },
   { "GL_RED_SCALE", 0x0D14 },
   { "GL_RED_BIAS", 0x0D15 },
   { "GL_GREEN_SCALE", 0x0D18 },
   { "GL_GREEN_BIAS", 0x0D19 },
   { "GL_BLUE_SCALE", 0x0D1A },
   { "GL_BLUE_BIAS", 0x0D1B },
   { "GL_ALPHA_SCALE", 0x0D1C },
   { "GL_ALPHA_BIAS", 0x0D1D },
   { "GL_DEPTH_SCALE", 0x0D1E },
   { "GL_DEPTH_BIAS", 0x0D1F },
   { "GL_PIXEL_MAP_S_TO_S_SIZE", 0x0CB1 },
   { "GL_PIXEL_MAP_I_TO_I_SIZE", 0x0CB0 },
   { "GL_PIXEL_MAP_I_TO_R_SIZE", 0x0CB2 },
   { "GL_PIXEL_MAP_I_TO_G_SIZE", 0x0CB3 },
   { "GL_PIXEL_MAP_I_TO_B_SIZE", 0x0CB4 },
   { "GL_PIXEL_MAP_I_TO_A_SIZE", 0x0CB5 },
   { "GL_PIXEL_MAP_R_TO_R_SIZE", 0x0CB6 },
   { "GL_PIXEL_MAP_G_TO_G_SIZE", 0x0CB7 },
   { "GL_PIXEL_MAP_B_TO_B_SIZE", 0x0CB8 },
   { "GL_PIXEL_MAP_A_TO_A_SIZE", 0x0CB9 },
   { "GL_PIXEL_MAP_S_TO_S", 0x0C71 },
   { "GL_PIXEL_MAP_I_TO_I", 0x0C70 },
   { "GL_PIXEL_MAP_I_TO_R", 0x0C72 },
   { "GL_PIXEL_MAP_I_TO_G", 0x0C73 },
   { "GL_PIXEL_MAP_I_TO_B", 0x0C74 },
   { "GL_PIXEL_MAP_I_TO_A", 0x0C75 },
   { "GL_PIXEL_MAP_R_TO_R", 0x0C76 },
   { "GL_PIXEL_MAP_G_TO_G", 0x0C77 },
   { "GL_PIXEL_MAP_B_TO_B", 0x0C78 },
   { "GL_PIXEL_MAP_A_TO_A", 0x0C79 },
   { "GL_PACK_ALIGNMENT", 0x0D05 },
   { "GL_PACK_LSB_FIRST", 0x0D01 },
   { "GL_PACK_ROW_LENGTH", 0x0D02 },
   { "GL_PACK_SKIP_PIXELS", 0x0D04 },
   { "GL_PACK_SKIP_ROWS", 0x0D03 },
   { "GL_PACK_SWAP_BYTES", 0x0D00 },
   { "GL_UNPACK_ALIGNMENT", 0x0CF5 },
   { "GL_UNPACK_LSB_FIRST", 0x0CF1 },
   { "GL_UNPACK_ROW_LENGTH", 0x0CF2 },
   { "GL_UNPACK_SKIP_PIXELS", 0x0CF4 },
   { "GL_UNPACK_SKIP_ROWS", 0x0CF3 },
   { "GL_UNPACK_SWAP_BYTES", 0x0CF0 },
   { "GL_ZOOM_X", 0x0D16 },
   { "GL_ZOOM_Y", 0x0D17 },

   /* Texture mapping */
   { "GL_TEXTURE_ENV", 0x2300 },
   { "GL_TEXTURE_ENV_MODE", 0x2200 },
   { "GL_TEXTURE_1D", 0x0DE0 },
   { "GL_TEXTURE_2D", 0x0DE1 },
   { "GL_TEXTURE_WRAP_S", 0x2802 },
   { "GL_TEXTURE_WRAP_T", 0x2803 },
   { "GL_TEXTURE_MAG_FILTER", 0x2800 },
   { "GL_TEXTURE_MIN_FILTER", 0x2801 },
   { "GL_TEXTURE_ENV_COLOR", 0x2201 },
   { "GL_TEXTURE_GEN_S", 0x0C60 },
   { "GL_TEXTURE_GEN_T", 0x0C61 },
   { "GL_TEXTURE_GEN_MODE", 0x2500 },
   { "GL_TEXTURE_BORDER_COLOR", 0x1004 },
   { "GL_TEXTURE_WIDTH", 0x1000 },
   { "GL_TEXTURE_HEIGHT", 0x1001 },
   { "GL_TEXTURE_BORDER", 0x1005 },
   { "GL_TEXTURE_COMPONENTS", 0x1003 },
   { "GL_TEXTURE_RED_SIZE", 0x805C },
   { "GL_TEXTURE_GREEN_SIZE", 0x805D },
   { "GL_TEXTURE_BLUE_SIZE", 0x805E },
   { "GL_TEXTURE_ALPHA_SIZE", 0x805F },
   { "GL_TEXTURE_LUMINANCE_SIZE", 0x8060 },
   { "GL_TEXTURE_INTENSITY_SIZE", 0x8061 },
   { "GL_NEAREST_MIPMAP_NEAREST", 0x2700 },
   { "GL_NEAREST_MIPMAP_LINEAR", 0x2702 },
   { "GL_LINEAR_MIPMAP_NEAREST", 0x2701 },
   { "GL_LINEAR_MIPMAP_LINEAR", 0x2703 },
   { "GL_OBJECT_LINEAR", 0x2401 },
   { "GL_OBJECT_PLANE", 0x2501 },
   { "GL_EYE_LINEAR", 0x2400 },
   { "GL_EYE_PLANE", 0x2502 },
   { "GL_SPHERE_MAP", 0x2402 },
   { "GL_DECAL", 0x2101 },
   { "GL_MODULATE", 0x2100 },
   { "GL_NEAREST", 0x2600 },
   { "GL_REPEAT", 0x2901 },
   { "GL_CLAMP", 0x2900 },
   { "GL_S", 0x2000 },
   { "GL_T", 0x2001 },
   { "GL_R", 0x2002 },
   { "GL_Q", 0x2003 },
   { "GL_TEXTURE_GEN_R", 0x0C62 },
   { "GL_TEXTURE_GEN_Q", 0x0C63 },

   /* GL 1.1 texturing */
   { "GL_PROXY_TEXTURE_1D", 0x8063 },
   { "GL_PROXY_TEXTURE_2D", 0x8064 },
   { "GL_TEXTURE_PRIORITY", 0x8066 },
   { "GL_TEXTURE_RESIDENT", 0x8067 },
   { "GL_TEXTURE_BINDING_1D", 0x8068 },
   { "GL_TEXTURE_BINDING_2D", 0x8069 },
   { "GL_TEXTURE_INTERNAL_FORMAT", 0x1003 },

   /* GL 1.2 texturing */
   { "GL_PACK_SKIP_IMAGES", 0x806B },
   { "GL_PACK_IMAGE_HEIGHT", 0x806C },
   { "GL_UNPACK_SKIP_IMAGES", 0x806D },
   { "GL_UNPACK_IMAGE_HEIGHT", 0x806E },
   { "GL_TEXTURE_3D", 0x806F },
   { "GL_PROXY_TEXTURE_3D", 0x8070 },
   { "GL_TEXTURE_DEPTH", 0x8071 },
   { "GL_TEXTURE_WRAP_R", 0x8072 },
   { "GL_MAX_3D_TEXTURE_SIZE", 0x8073 },
   { "GL_TEXTURE_BINDING_3D", 0x806A },

   /* Internal texture formats (GL 1.1) */
   { "GL_ALPHA4", 0x803B },
   { "GL_ALPHA8", 0x803C },
   { "GL_ALPHA12", 0x803D },
   { "GL_ALPHA16", 0x803E },
   { "GL_LUMINANCE4", 0x803F },
   { "GL_LUMINANCE8", 0x8040 },
   { "GL_LUMINANCE12", 0x8041 },
   { "GL_LUMINANCE16", 0x8042 },
   { "GL_LUMINANCE4_ALPHA4", 0x8043 },
   { "GL_LUMINANCE6_ALPHA2", 0x8044 },
   { "GL_LUMINANCE8_ALPHA8", 0x8045 },
   { "GL_LUMINANCE12_ALPHA4", 0x8046 },
   { "GL_LUMINANCE12_ALPHA12", 0x8047 },
   { "GL_LUMINANCE16_ALPHA16", 0x8048 },
   { "GL_INTENSITY", 0x8049 },
   { "GL_INTENSITY4", 0x804A },
   { "GL_INTENSITY8", 0x804B },
   { "GL_INTENSITY12", 0x804C },
   { "GL_INTENSITY16", 0x804D },
   { "GL_R3_G3_B2", 0x2A10 },
   { "GL_RGB4", 0x804F },
   { "GL_RGB5", 0x8050 },
   { "GL_RGB8", 0x8051 },
   { "GL_RGB10", 0x8052 },
   { "GL_RGB12", 0x8053 },
   { "GL_RGB16", 0x8054 },
   { "GL_RGBA2", 0x8055 },
   { "GL_RGBA4", 0x8056 },
   { "GL_RGB5_A1", 0x8057 },
   { "GL_RGBA8", 0x8058 },
   { "GL_RGB10_A2", 0x8059 },
   { "GL_RGBA12", 0x805A },
   { "GL_RGBA16", 0x805B },

   /* Utility */
   { "GL_VENDOR", 0x1F00 },
   { "GL_RENDERER", 0x1F01 },
   { "GL_VERSION", 0x1F02 },
   { "GL_EXTENSIONS", 0x1F03 },

   /* Errors */
   { "GL_INVALID_VALUE", 0x0501 },
   { "GL_INVALID_ENUM", 0x0500 },
   { "GL_INVALID_OPERATION", 0x0502 },
   { "GL_STACK_OVERFLOW", 0x0503 },
   { "GL_STACK_UNDERFLOW", 0x0504 },
   { "GL_OUT_OF_MEMORY", 0x0505 },

   /*
    * Extensions
    */

   { "GL_CONSTANT_COLOR_EXT", 0x8001 },
   { "GL_ONE_MINUS_CONSTANT_COLOR_EXT", 0x8002 },
   { "GL_CONSTANT_ALPHA_EXT", 0x8003 },
   { "GL_ONE_MINUS_CONSTANT_ALPHA_EXT", 0x8004 },
   { "GL_BLEND_EQUATION_EXT", 0x8009 },
   { "GL_MIN_EXT", 0x8007 },
   { "GL_MAX_EXT", 0x8008 },
   { "GL_FUNC_ADD_EXT", 0x8006 },
   { "GL_FUNC_SUBTRACT_EXT", 0x800A },
   { "GL_FUNC_REVERSE_SUBTRACT_EXT", 0x800B },
   { "GL_BLEND_COLOR_EXT", 0x8005 },

   { "GL_POLYGON_OFFSET_EXT", 0x8037 },
   { "GL_POLYGON_OFFSET_FACTOR_EXT", 0x8038 },
   { "GL_POLYGON_OFFSET_BIAS_EXT", 0x8039 },


   { "GL_VERTEX_ARRAY_EXT", 0x8074 },
   { "GL_NORMAL_ARRAY_EXT", 0x8075 },
   { "GL_COLOR_ARRAY_EXT", 0x8076 },
   { "GL_INDEX_ARRAY_EXT", 0x8077 },
   { "GL_TEXTURE_COORD_ARRAY_EXT", 0x8078 },
   { "GL_EDGE_FLAG_ARRAY_EXT", 0x8079 },
   { "GL_VERTEX_ARRAY_SIZE_EXT", 0x807A },
   { "GL_VERTEX_ARRAY_TYPE_EXT", 0x807B },
   { "GL_VERTEX_ARRAY_STRIDE_EXT", 0x807C },
   { "GL_VERTEX_ARRAY_COUNT_EXT", 0x807D },
   { "GL_NORMAL_ARRAY_TYPE_EXT", 0x807E },
   { "GL_NORMAL_ARRAY_STRIDE_EXT", 0x807F },
   { "GL_NORMAL_ARRAY_COUNT_EXT", 0x8080 },
   { "GL_COLOR_ARRAY_SIZE_EXT", 0x8081 },
   { "GL_COLOR_ARRAY_TYPE_EXT", 0x8082 },
   { "GL_COLOR_ARRAY_STRIDE_EXT", 0x8083 },
   { "GL_COLOR_ARRAY_COUNT_EXT", 0x8084 },
   { "GL_INDEX_ARRAY_TYPE_EXT", 0x8085 },
   { "GL_INDEX_ARRAY_STRIDE_EXT", 0x8086 },
   { "GL_INDEX_ARRAY_COUNT_EXT", 0x8087 },
   { "GL_TEXTURE_COORD_ARRAY_SIZE_EXT", 0x8088 },
   { "GL_TEXTURE_COORD_ARRAY_TYPE_EXT", 0x8089 },
   { "GL_TEXTURE_COORD_ARRAY_STRIDE_EXT", 0x808A },
   { "GL_TEXTURE_COORD_ARRAY_COUNT_EXT", 0x808B },
   { "GL_EDGE_FLAG_ARRAY_STRIDE_EXT", 0x808C },
   { "GL_EDGE_FLAG_ARRAY_COUNT_EXT", 0x808D },
   { "GL_VERTEX_ARRAY_POINTER_EXT", 0x808E },
   { "GL_NORMAL_ARRAY_POINTER_EXT", 0x808F },
   { "GL_COLOR_ARRAY_POINTER_EXT", 0x8090 },
   { "GL_INDEX_ARRAY_POINTER_EXT", 0x8091 },
   { "GL_TEXTURE_COORD_ARRAY_POINTER_EXT", 0x8092 },
   { "GL_EDGE_FLAG_ARRAY_POINTER_EXT", 0x8093 },

   { "GL_TEXTURE_PRIORITY_EXT", 0x8066 },
   { "GL_TEXTURE_RESIDENT_EXT", 0x8067 },
   { "GL_TEXTURE_1D_BINDING_EXT", 0x8068 },
   { "GL_TEXTURE_2D_BINDING_EXT", 0x8069 },

   { "GL_PACK_SKIP_IMAGES_EXT", 0x806B },
   { "GL_PACK_IMAGE_HEIGHT_EXT", 0x806C },
   { "GL_UNPACK_SKIP_IMAGES_EXT", 0x806D },
   { "GL_UNPACK_IMAGE_HEIGHT_EXT", 0x806E },
   { "GL_TEXTURE_3D_EXT", 0x806F },
   { "GL_PROXY_TEXTURE_3D_EXT", 0x8070 },
   { "GL_TEXTURE_DEPTH_EXT", 0x8071 },
   { "GL_TEXTURE_WRAP_R_EXT", 0x8072 },
   { "GL_MAX_3D_TEXTURE_SIZE_EXT", 0x8073 },
   { "GL_TEXTURE_3D_BINDING_EXT", 0x806A },

   { "GL_TABLE_TOO_LARGE_EXT", 0x8031 },
   { "GL_COLOR_TABLE_FORMAT_EXT", 0x80D8 },
   { "GL_COLOR_TABLE_WIDTH_EXT", 0x80D9 },
   { "GL_COLOR_TABLE_RED_SIZE_EXT", 0x80DA },
   { "GL_COLOR_TABLE_GREEN_SIZE_EXT", 0x80DB },
   { "GL_COLOR_TABLE_BLUE_SIZE_EXT", 0x80DC },
   { "GL_COLOR_TABLE_ALPHA_SIZE_EXT", 0x80DD },
   { "GL_COLOR_TABLE_LUMINANCE_SIZE_EXT", 0x80DE },
   { "GL_COLOR_TABLE_INTENSITY_SIZE_EXT", 0x80DF },
   { "GL_TEXTURE_INDEX_SIZE_EXT", 0x80ED },
   { "GL_COLOR_INDEX1_EXT", 0x80E2 },
   { "GL_COLOR_INDEX2_EXT", 0x80E3 },
   { "GL_COLOR_INDEX4_EXT", 0x80E4 },
   { "GL_COLOR_INDEX8_EXT", 0x80E5 },
   { "GL_COLOR_INDEX12_EXT", 0x80E6 },
   { "GL_COLOR_INDEX16_EXT", 0x80E7 },

   { "GL_SHARED_TEXTURE_PALETTE_EXT", 0x81FB },

   { "GL_POINT_SIZE_MIN_EXT", 0x8126 },
   { "GL_POINT_SIZE_MAX_EXT", 0x8127 },
   { "GL_POINT_FADE_THRESHOLD_SIZE_EXT", 0x8128 },
   { "GL_DISTANCE_ATTENUATION_EXT", 0x8129 },

   { "GL_RESCALE_NORMAL_EXT", 0x803A },

   { "GL_ABGR_EXT", 0x8000 },

   { "GL_INCR_WRAP_EXT", 0x8507 },
   { "GL_DECR_WRAP_EXT", 0x8508 },

   { "GL_CLAMP_TO_EDGE_SGIS", 0x812F },

   { "GL_BLEND_DST_RGB_INGR", 0x80C8 },
   { "GL_BLEND_SRC_RGB_INGR", 0x80C9 },
   { "GL_BLEND_DST_ALPHA_INGR", 0x80CA },
   { "GL_BLEND_SRC_ALPHA_INGR", 0x80CB },

   { "GL_RESCALE_NORMAL", 0x803A },
   { "GL_CLAMP_TO_EDGE", 0x812F },
   { "GL_MAX_ELEMENTS_VERTICES", 0xF0E8 },
   { "GL_MAX_ELEMENTS_INDICES", 0xF0E9 },
   { "GL_BGR", 0x80E0 },
   { "GL_BGRA", 0x80E1 },
   { "GL_UNSIGNED_BYTE_3_3_2", 0x8032 },
   { "GL_UNSIGNED_BYTE_2_3_3_REV", 0x8362 },
   { "GL_UNSIGNED_SHORT_5_6_5", 0x8363 },
   { "GL_UNSIGNED_SHORT_5_6_5_REV", 0x8364 },
   { "GL_UNSIGNED_SHORT_4_4_4_4", 0x8033 },
   { "GL_UNSIGNED_SHORT_4_4_4_4_REV", 0x8365 },
   { "GL_UNSIGNED_SHORT_5_5_5_1", 0x8034 },
   { "GL_UNSIGNED_SHORT_1_5_5_5_REV", 0x8366 },
   { "GL_UNSIGNED_INT_8_8_8_8", 0x8035 },
   { "GL_UNSIGNED_INT_8_8_8_8_REV", 0x8367 },
   { "GL_UNSIGNED_INT_10_10_10_2", 0x8036 },
   { "GL_UNSIGNED_INT_2_10_10_10_REV", 0x8368 },
   { "GL_LIGHT_MODEL_COLOR_CONTROL", 0x81F8 },
   { "GL_SINGLE_COLOR", 0x81F9 },
   { "GL_SEPARATE_SPECULAR_COLOR", 0x81FA },
   { "GL_TEXTURE_MIN_LOD", 0x813A },
   { "GL_TEXTURE_MAX_LOD", 0x813B },
   { "GL_TEXTURE_BASE_LEVEL", 0x813C },
   { "GL_TEXTURE_MAX_LEVEL", 0x813D },

   { "GL_TEXTURE0_ARB", 0x84C0 },
   { "GL_TEXTURE1_ARB", 0x84C1 },
   { "GL_TEXTURE2_ARB", 0x84C2 },
   { "GL_TEXTURE3_ARB", 0x84C3 },
   { "GL_ACTIVE_TEXTURE_ARB", 0x84E0 },
   { "GL_CLIENT_ACTIVE_TEXTURE_ARB", 0x84E1 },
   { "GL_MAX_TEXTURE_UNITS_ARB", 0x84E2 },

   { "GL_NORMAL_MAP_NV", 0x8511 },
   { "GL_REFLECTION_MAP_NV", 0x8512 },

   { "GL_PREFER_DOUBLEBUFFER_HINT_PGI", 107000 },
   { "GL_STRICT_DEPTHFUNC_HINT_PGI", 107030 },
   { "GL_STRICT_LIGHTING_HINT_PGI", 107031 },
   { "GL_STRICT_SCISSOR_HINT_PGI", 107032 },
   { "GL_FULL_STIPPLE_HINT_PGI", 107033 },
   { "GL_NATIVE_GRAPHICS_BEGIN_HINT_PGI", 107011 },
   { "GL_NATIVE_GRAPHICS_END_HINT_PGI", 107012 },
   { "GL_CONSERVE_MEMORY_HINT_PGI", 107005 },
   { "GL_RECLAIM_MEMORY_HINT_PGI", 107006 },
   { "GL_ALWAYS_FAST_HINT_PGI", 107020 },
   { "GL_ALWAYS_SOFT_HINT_PGI", 107021 },
   { "GL_ALLOW_DRAW_OBJ_HINT_PGI", 107022 },
   { "GL_ALLOW_DRAW_WIN_HINT_PGI", 107023 },
   { "GL_ALLOW_DRAW_FRG_HINT_PGI", 107024 },
   { "GL_ALLOW_DRAW_SPN_HINT_PGI", 107024 },
   { "GL_ALLOW_DRAW_MEM_HINT_PGI", 107025 },
   { "GL_CLIP_NEAR_HINT_PGI", 107040 },
   { "GL_CLIP_FAR_HINT_PGI", 107041 },
   { "GL_WIDE_LINE_HINT_PGI", 107042 },
   { "GL_BACK_NORMALS_HINT_PGI", 107043 },
   { "GL_NATIVE_GRAPHICS_HANDLE_PGI", 107010 },

   /* GL_EXT_compiled_vertex_array */
   { "GL_ARRAY_ELEMENT_LOCK_FIRST_SGI", 0x81A8},
   { "GL_ARRAY_ELEMENT_LOCK_COUNT_SGI", 0x81A9},

   /* GL_EXT_clip_volume_hint */
   { "GL_CLIP_VOLUME_CLIPPING_HINT_EXT", 0x80F0}

};

#define Elements(x) sizeof(x)/sizeof(*x)

typedef int (GLWINAPIV *cfunc)(const void *, const void *);

static enum_elt **index1 = 0;
static int sorted = 0;

static int compar_name( const enum_elt *a, const enum_elt *b ) 
{
   return strcmp(a->c, b->c);
}


/* note the extra level of indirection
 */
static int compar_nr( const enum_elt **a, const enum_elt **b ) 
{
   return (*a)->n - (*b)->n;
}


static void sort_enums( void )
{
   int i;
   index1 = (enum_elt **)MALLOC( Elements(all_enums) * sizeof(enum_elt *) );
   sorted = 1;

   qsort( all_enums, Elements(all_enums), sizeof(*all_enums), 
	  (cfunc) compar_name );

   for (i = 0 ; i < Elements(all_enums) ; i++) 
      index1[i] = &all_enums[i];

   qsort( index1, Elements(all_enums), sizeof(*index1), (cfunc) compar_nr );
}



int gl_lookup_enum_by_name( const char *symbol )
{
   enum_elt tmp;
   enum_elt *e;

   if (!sorted) 
      sort_enums();

   if (!symbol) 
      return 0;

   tmp.c = symbol;
   e = (enum_elt *)bsearch( &tmp, all_enums, Elements(all_enums), 
			    sizeof(*all_enums), (cfunc) compar_name );

   return e ? e->n : -1;
}


const char *gl_lookup_enum_by_nr( int nr )
{
   enum_elt tmp, *e, **f;

   if (!sorted) 
      sort_enums();

   tmp.n = nr;
   e = &tmp;

   f = (enum_elt **)bsearch( &e, index1, Elements(all_enums), 
			     sizeof(*index1), (cfunc) compar_nr );

   return f ? (*f)->c : "(unknown)";
}


#if 0
int main()
{
   int i;
   static const char *test[] = {
      "GL_POLYGON",
      "GL_TRUE",
      "GL_BANANA",
      "GL_REFLECTION_MAP_NV",
   };

   for (i = 0 ; i < Elements(test) ; i++) {
      int d = gl_lookup_enum_by_name( test[i] );
      printf("%s --> %d --> %s\n", test[i], d, gl_lookup_enum_by_nr( d ));
   }       
}
#endif
lu.dst.write = 1; alu.last = 1; if ((r = r600_bc_add_alu(ctx->bc, &alu))) return r; break; } default: R600_ERR("unsupported file %d declaration\n", d->Declaration.File); return -EINVAL; } return 0; } static int r600_get_temp(struct r600_shader_ctx *ctx) { return ctx->temp_reg + ctx->max_driver_temp_used++; } /* * for evergreen we need to scan the shader to find the number of GPRs we need to * reserve for interpolation. * * we need to know if we are going to emit * any centroid inputs * if perspective and linear are required */ static int evergreen_gpr_count(struct r600_shader_ctx *ctx) { int i; int num_baryc; ctx->input_linear = FALSE; ctx->input_perspective = FALSE; ctx->input_centroid = FALSE; ctx->num_interp_gpr = 1; /* any centroid inputs */ for (i = 0; i < ctx->info.num_inputs; i++) { /* skip position/face */ if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION || ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE) continue; if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR) ctx->input_linear = TRUE; if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE) ctx->input_perspective = TRUE; if (ctx->info.input_centroid[i]) ctx->input_centroid = TRUE; } num_baryc = 0; /* ignoring sample for now */ if (ctx->input_perspective) num_baryc++; if (ctx->input_linear) num_baryc++; if (ctx->input_centroid) num_baryc *= 2; ctx->num_interp_gpr += (num_baryc + 1) >> 1; /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */ return ctx->num_interp_gpr; } static void tgsi_src(struct r600_shader_ctx *ctx, const struct tgsi_full_src_register *tgsi_src, struct r600_shader_src *r600_src) { memset(r600_src, 0, sizeof(*r600_src)); r600_src->swizzle[0] = tgsi_src->Register.SwizzleX; r600_src->swizzle[1] = tgsi_src->Register.SwizzleY; r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ; r600_src->swizzle[3] = tgsi_src->Register.SwizzleW; r600_src->neg = tgsi_src->Register.Negate; r600_src->abs = tgsi_src->Register.Absolute; if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) { int index; if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) && (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) && (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) { index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX; r600_bc_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg); if (r600_src->sel != V_SQ_ALU_SRC_LITERAL) return; } index = tgsi_src->Register.Index; r600_src->sel = V_SQ_ALU_SRC_LITERAL; memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value)); } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) { /* assume we wan't TGSI_SEMANTIC_INSTANCEID here */ r600_src->swizzle[0] = 3; r600_src->swizzle[1] = 3; r600_src->swizzle[2] = 3; r600_src->swizzle[3] = 3; r600_src->sel = 0; } else { if (tgsi_src->Register.Indirect) r600_src->rel = V_SQ_REL_RELATIVE; r600_src->sel = tgsi_src->Register.Index; r600_src->sel += ctx->file_offset[tgsi_src->Register.File]; } } static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg) { struct r600_bc_vtx vtx; unsigned int ar_reg; int r; if (offset) { struct r600_bc_alu alu; memset(&alu, 0, sizeof(alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT); alu.src[0].sel = ctx->ar_reg; alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; alu.src[1].value = offset; alu.dst.sel = dst_reg; alu.dst.write = 1; alu.last = 1; if ((r = r600_bc_add_alu(ctx->bc, &alu))) return r; ar_reg = dst_reg; } else { ar_reg = ctx->ar_reg; } memset(&vtx, 0, sizeof(vtx)); vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */ vtx.src_gpr = ar_reg; vtx.mega_fetch_count = 16; vtx.dst_gpr = dst_reg; vtx.dst_sel_x = 0; /* SEL_X */ vtx.dst_sel_y = 1; /* SEL_Y */ vtx.dst_sel_z = 2; /* SEL_Z */ vtx.dst_sel_w = 3; /* SEL_W */ vtx.data_format = FMT_32_32_32_32_FLOAT; vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */ vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */ vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */ vtx.endian = r600_endian_swap(32); if ((r = r600_bc_add_vtx(ctx->bc, &vtx))) return r; return 0; } static int tgsi_split_constant(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, j, k, nconst, r; for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) { if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) { nconst++; } tgsi_src(ctx, &inst->Src[i], &ctx->src[i]); } for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) { if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) { continue; } if (ctx->src[i].rel) { int treg = r600_get_temp(ctx); if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].sel - 512, treg))) return r; ctx->src[i].sel = treg; ctx->src[i].rel = 0; j--; } else if (j > 0) { int treg = r600_get_temp(ctx); for (k = 0; k < 4; k++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = ctx->src[i].sel; alu.src[0].chan = k; alu.src[0].rel = ctx->src[i].rel; alu.dst.sel = treg; alu.dst.chan = k; alu.dst.write = 1; if (k == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } ctx->src[i].sel = treg; ctx->src[i].rel =0; j--; } } return 0; } /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */ static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, j, k, nliteral, r; for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) { if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) { nliteral++; } } for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) { if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) { int treg = r600_get_temp(ctx); for (k = 0; k < 4; k++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = ctx->src[i].sel; alu.src[0].chan = k; alu.src[0].value = ctx->src[i].value[k]; alu.dst.sel = treg; alu.dst.chan = k; alu.dst.write = 1; if (k == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } ctx->src[i].sel = treg; j--; } } return 0; } static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader) { struct tgsi_full_immediate *immediate; struct tgsi_full_property *property; struct r600_shader_ctx ctx; struct r600_bc_output output[32]; unsigned output_done, noutput; unsigned opcode; int i, r = 0, pos0; ctx.bc = &shader->bc; ctx.shader = shader; r = r600_bc_init(ctx.bc, shader->family); if (r) return r; ctx.tokens = tokens; tgsi_scan_shader(tokens, &ctx.info); tgsi_parse_init(&ctx.parse, tokens); ctx.type = ctx.parse.FullHeader.Processor.Processor; shader->processor_type = ctx.type; ctx.bc->type = shader->processor_type; /* register allocations */ /* Values [0,127] correspond to GPR[0..127]. * Values [128,159] correspond to constant buffer bank 0 * Values [160,191] correspond to constant buffer bank 1 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG) * Values [256,287] correspond to constant buffer bank 2 (EG) * Values [288,319] correspond to constant buffer bank 3 (EG) * Other special values are shown in the list below. * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+) * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+) * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+) * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+) * 248 SQ_ALU_SRC_0: special constant 0.0. * 249 SQ_ALU_SRC_1: special constant 1.0 float. * 250 SQ_ALU_SRC_1_INT: special constant 1 integer. * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer. * 252 SQ_ALU_SRC_0_5: special constant 0.5 float. * 253 SQ_ALU_SRC_LITERAL: literal constant. * 254 SQ_ALU_SRC_PV: previous vector result. * 255 SQ_ALU_SRC_PS: previous scalar result. */ for (i = 0; i < TGSI_FILE_COUNT; i++) { ctx.file_offset[i] = 0; } if (ctx.type == TGSI_PROCESSOR_VERTEX) { ctx.file_offset[TGSI_FILE_INPUT] = 1; if (ctx.bc->chiprev >= CHIPREV_EVERGREEN) { r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS); } else { r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS); } } if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev >= CHIPREV_EVERGREEN) { ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx); } ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] + ctx.info.file_count[TGSI_FILE_INPUT]; ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] + ctx.info.file_count[TGSI_FILE_OUTPUT]; /* Outside the GPR range. This will be translated to one of the * kcache banks later. */ ctx.file_offset[TGSI_FILE_CONSTANT] = 512; ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL; ctx.ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] + ctx.info.file_count[TGSI_FILE_TEMPORARY]; ctx.temp_reg = ctx.ar_reg + 1; ctx.nliterals = 0; ctx.literals = NULL; shader->fs_write_all = FALSE; while (!tgsi_parse_end_of_tokens(&ctx.parse)) { tgsi_parse_token(&ctx.parse); switch (ctx.parse.FullToken.Token.Type) { case TGSI_TOKEN_TYPE_IMMEDIATE: immediate = &ctx.parse.FullToken.FullImmediate; ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16); if(ctx.literals == NULL) { r = -ENOMEM; goto out_err; } ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint; ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint; ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint; ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint; ctx.nliterals++; break; case TGSI_TOKEN_TYPE_DECLARATION: r = tgsi_declaration(&ctx); if (r) goto out_err; break; case TGSI_TOKEN_TYPE_INSTRUCTION: r = tgsi_is_supported(&ctx); if (r) goto out_err; ctx.max_driver_temp_used = 0; /* reserve first tmp for everyone */ r600_get_temp(&ctx); opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode; if ((r = tgsi_split_constant(&ctx))) goto out_err; if ((r = tgsi_split_literal_constant(&ctx))) goto out_err; if (ctx.bc->chiprev == CHIPREV_CAYMAN) ctx.inst_info = &cm_shader_tgsi_instruction[opcode]; else if (ctx.bc->chiprev >= CHIPREV_EVERGREEN) ctx.inst_info = &eg_shader_tgsi_instruction[opcode]; else ctx.inst_info = &r600_shader_tgsi_instruction[opcode]; r = ctx.inst_info->process(&ctx); if (r) goto out_err; break; case TGSI_TOKEN_TYPE_PROPERTY: property = &ctx.parse.FullToken.FullProperty; if (property->Property.PropertyName == TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) { if (property->u[0].Data == 1) shader->fs_write_all = TRUE; } break; default: R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type); r = -EINVAL; goto out_err; } } /* export output */ noutput = shader->noutput; for (i = 0, pos0 = 0; i < noutput; i++) { memset(&output[i], 0, sizeof(struct r600_bc_output)); output[i].gpr = shader->output[i].gpr; output[i].elem_size = 3; output[i].swizzle_x = 0; output[i].swizzle_y = 1; output[i].swizzle_z = 2; output[i].swizzle_w = 3; output[i].burst_count = 1; output[i].barrier = 1; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM; output[i].array_base = i - pos0; output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT); switch (ctx.type) { case TGSI_PROCESSOR_VERTEX: if (shader->output[i].name == TGSI_SEMANTIC_POSITION) { output[i].array_base = 60; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS; /* position doesn't count in array_base */ pos0++; } if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) { output[i].array_base = 61; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS; /* position doesn't count in array_base */ pos0++; } break; case TGSI_PROCESSOR_FRAGMENT: if (shader->output[i].name == TGSI_SEMANTIC_COLOR) { output[i].array_base = shader->output[i].sid; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL; } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) { output[i].array_base = 61; output[i].swizzle_x = 2; output[i].swizzle_y = 7; output[i].swizzle_z = output[i].swizzle_w = 7; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL; } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) { output[i].array_base = 61; output[i].swizzle_x = 7; output[i].swizzle_y = 1; output[i].swizzle_z = output[i].swizzle_w = 7; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL; } else { R600_ERR("unsupported fragment output name %d\n", shader->output[i].name); r = -EINVAL; goto out_err; } break; default: R600_ERR("unsupported processor type %d\n", ctx.type); r = -EINVAL; goto out_err; } } /* add fake param output for vertex shader if no param is exported */ if (ctx.type == TGSI_PROCESSOR_VERTEX) { for (i = 0, pos0 = 0; i < noutput; i++) { if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) { pos0 = 1; break; } } if (!pos0) { memset(&output[i], 0, sizeof(struct r600_bc_output)); output[i].gpr = 0; output[i].elem_size = 3; output[i].swizzle_x = 0; output[i].swizzle_y = 1; output[i].swizzle_z = 2; output[i].swizzle_w = 3; output[i].burst_count = 1; output[i].barrier = 1; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM; output[i].array_base = 0; output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT); noutput++; } } /* add fake pixel export */ if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) { memset(&output[0], 0, sizeof(struct r600_bc_output)); output[0].gpr = 0; output[0].elem_size = 3; output[0].swizzle_x = 7; output[0].swizzle_y = 7; output[0].swizzle_z = 7; output[0].swizzle_w = 7; output[0].burst_count = 1; output[0].barrier = 1; output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL; output[0].array_base = 0; output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT); noutput++; } /* set export done on last export of each type */ for (i = noutput - 1, output_done = 0; i >= 0; i--) { if (ctx.bc->chiprev < CHIPREV_CAYMAN) { if (i == (noutput - 1)) { output[i].end_of_program = 1; } } if (!(output_done & (1 << output[i].type))) { output_done |= (1 << output[i].type); output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE); } } /* add output to bytecode */ for (i = 0; i < noutput; i++) { r = r600_bc_add_output(ctx.bc, &output[i]); if (r) goto out_err; } /* add program end */ if (ctx.bc->chiprev == CHIPREV_CAYMAN) cm_bc_add_cf_end(ctx.bc); free(ctx.literals); tgsi_parse_free(&ctx.parse); return 0; out_err: free(ctx.literals); tgsi_parse_free(&ctx.parse); return r; } static int tgsi_unsupported(struct r600_shader_ctx *ctx) { R600_ERR("%s tgsi opcode unsupported\n", tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode)); return -EINVAL; } static int tgsi_end(struct r600_shader_ctx *ctx) { return 0; } static void r600_bc_src(struct r600_bc_alu_src *bc_src, const struct r600_shader_src *shader_src, unsigned chan) { bc_src->sel = shader_src->sel; bc_src->chan = shader_src->swizzle[chan]; bc_src->neg = shader_src->neg; bc_src->abs = shader_src->abs; bc_src->rel = shader_src->rel; bc_src->value = shader_src->value[bc_src->chan]; } static void tgsi_dst(struct r600_shader_ctx *ctx, const struct tgsi_full_dst_register *tgsi_dst, unsigned swizzle, struct r600_bc_alu_dst *r600_dst) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; r600_dst->sel = tgsi_dst->Register.Index; r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File]; r600_dst->chan = swizzle; r600_dst->write = 1; if (tgsi_dst->Register.Indirect) r600_dst->rel = V_SQ_REL_RELATIVE; if (inst->Instruction.Saturate) { r600_dst->clamp = 1; } } static int tgsi_last_instruction(unsigned writemask) { int i, lasti = 0; for (i = 0; i < 4; i++) { if (writemask & (1 << i)) { lasti = i; } } return lasti; } static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, j, r; int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.inst = ctx->inst_info->r600_opcode; if (!swap) { for (j = 0; j < inst->Instruction.NumSrcRegs; j++) { r600_bc_src(&alu.src[j], &ctx->src[j], i); } } else { r600_bc_src(&alu.src[0], &ctx->src[1], i); r600_bc_src(&alu.src[1], &ctx->src[0], i); } /* handle some special cases */ switch (ctx->inst_info->tgsi_opcode) { case TGSI_OPCODE_SUB: alu.src[1].neg = 1; break; case TGSI_OPCODE_ABS: alu.src[0].abs = 1; if (alu.src[0].neg) alu.src[0].neg = 0; break; default: break; } if (i == lasti) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_op2(struct r600_shader_ctx *ctx) { return tgsi_op2_s(ctx, 0); } static int tgsi_op2_swap(struct r600_shader_ctx *ctx) { return tgsi_op2_s(ctx, 1); } static int cayman_emit_float_instr(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; int i, j, r; struct r600_bc_alu alu; int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3; for (i = 0 ; i < last_slot; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; for (j = 0; j < inst->Instruction.NumSrcRegs; j++) { r600_bc_src(&alu.src[j], &ctx->src[j], 0); } tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; if (i == last_slot - 1) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } /* * r600 - trunc to -PI..PI range * r700 - normalize by dividing by 2PI * see fdo bug 27901 */ static int tgsi_setup_trig(struct r600_shader_ctx *ctx) { static float half_inv_pi = 1.0 /(3.1415926535 * 2); static float double_pi = 3.1415926535 * 2; static float neg_pi = -3.1415926535; int r; struct r600_bc_alu alu; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.dst.chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; alu.src[1].chan = 0; alu.src[1].value = *(uint32_t *)&half_inv_pi; alu.src[2].sel = V_SQ_ALU_SRC_0_5; alu.src[2].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT); alu.dst.chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.dst.chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; alu.src[1].chan = 0; alu.src[2].sel = V_SQ_ALU_SRC_LITERAL; alu.src[2].chan = 0; if (ctx->bc->chiprev == CHIPREV_R600) { alu.src[1].value = *(uint32_t *)&double_pi; alu.src[2].value = *(uint32_t *)&neg_pi; } else { alu.src[1].sel = V_SQ_ALU_SRC_1; alu.src[2].sel = V_SQ_ALU_SRC_0_5; alu.src[2].neg = 1; } alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; return 0; } static int cayman_trig(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3; int i, r; r = tgsi_setup_trig(ctx); if (r) return r; for (i = 0; i < last_slot; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; alu.dst.chan = i; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; if (i == last_slot - 1) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_trig(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); r = tgsi_setup_trig(ctx); if (r) return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; alu.dst.chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* replicate result */ for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = ctx->temp_reg; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (i == lasti) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_scs(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; /* We'll only need the trig stuff if we are going to write to the * X or Y components of the destination vector. */ if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) { r = tgsi_setup_trig(ctx); if (r) return r; } /* dst.x = COS */ if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) { if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0 ; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (i == 0) alu.dst.write = 1; else alu.dst.write = 0; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS); tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } /* dst.y = SIN */ if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) { if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0 ; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (i == 1) alu.dst.write = 1; else alu.dst.write = 0; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN); tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } /* dst.z = 0.0; */ if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst); alu.src[0].sel = V_SQ_ALU_SRC_0; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* dst.w = 1.0; */ if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_kill(struct r600_shader_ctx *ctx) { struct r600_bc_alu alu; int i, r; for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; alu.dst.chan = i; alu.src[0].sel = V_SQ_ALU_SRC_0; if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) { alu.src[1].sel = V_SQ_ALU_SRC_1; alu.src[1].neg = 1; } else { r600_bc_src(&alu.src[1], &ctx->src[0], i); } if (i == 3) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* kill must be last in ALU */ ctx->bc->force_add_cf = 1; ctx->shader->uses_kill = TRUE; return 0; } static int tgsi_lit(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int r; /* dst.x, <- 1.0 */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/ alu.src[0].chan = 0; tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* dst.y = max(src.x, 0.0) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/ alu.src[1].chan = 0; tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* dst.w, <- 1.0 */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; if (inst->Dst[0].Register.WriteMask & (1 << 2)) { int chan; int sel; int i; if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { /* dst.z = log(src.y) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED); r600_bc_src(&alu.src[0], &ctx->src[0], 1); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (i == 2) { alu.dst.write = 1; alu.last = 1; } else alu.dst.write = 0; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { /* dst.z = log(src.y) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED); r600_bc_src(&alu.src[0], &ctx->src[0], 1); tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst); alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } chan = alu.dst.chan; sel = alu.dst.sel; /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT); r600_bc_src(&alu.src[0], &ctx->src[0], 3); alu.src[1].sel = sel; alu.src[1].chan = chan; r600_bc_src(&alu.src[2], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = 0; alu.dst.write = 1; alu.is_op3 = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { /* dst.z = exp(tmp.x) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (i == 2) { alu.dst.write = 1; alu.last = 1; } else alu.dst.write = 0; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { /* dst.z = exp(tmp.x) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst); alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } return 0; } static int tgsi_rsq(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; memset(&alu, 0, sizeof(struct r600_bc_alu)); /* FIXME: * For state trackers other than OpenGL, we'll want to use * _RECIPSQRT_IEEE instead. */ alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED); for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { r600_bc_src(&alu.src[i], &ctx->src[i], 0); alu.src[i].abs = 1; } alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* replicate result */ return tgsi_helper_tempx_replicate(ctx); } static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.src[0].sel = ctx->temp_reg; alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.dst.chan = i; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; if (i == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { r600_bc_src(&alu.src[i], &ctx->src[i], 0); } alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* replicate result */ return tgsi_helper_tempx_replicate(ctx); } static int cayman_pow(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; int i, r; struct r600_bc_alu alu; int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3; for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* b * LOG2(a) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); r600_bc_src(&alu.src[0], &ctx->src[1], 0); alu.src[1].sel = ctx->temp_reg; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; for (i = 0; i < last_slot; i++) { /* POW(a,b) = EXP2(b * LOG2(a))*/ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; if (i == last_slot - 1) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_pow(struct r600_shader_ctx *ctx) { struct r600_bc_alu alu; int r; /* LOG2(a) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* b * LOG2(a) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); r600_bc_src(&alu.src[0], &ctx->src[1], 0); alu.src[1].sel = ctx->temp_reg; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* POW(a,b) = EXP2(b * LOG2(a))*/ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; return tgsi_helper_tempx_replicate(ctx); } static int tgsi_ssg(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; /* tmp = (src > 0 ? 1 : src) */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT); alu.is_op3 = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; r600_bc_src(&alu.src[0], &ctx->src[0], i); alu.src[1].sel = V_SQ_ALU_SRC_1; r600_bc_src(&alu.src[2], &ctx->src[0], i); if (i == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* dst = (-tmp > 0 ? -1 : tmp) */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT); alu.is_op3 = 1; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = i; alu.src[0].neg = 1; alu.src[1].sel = V_SQ_ALU_SRC_1; alu.src[1].neg = 1; alu.src[2].sel = ctx->temp_reg; alu.src[2].chan = i; if (i == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst) { struct r600_bc_alu alu; int i, r; for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); if (!(inst->Dst[0].Register.WriteMask & (1 << i))) { alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP); alu.dst.chan = i; } else { alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = i; } if (i == 3) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_op3(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, j, r; int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; for (j = 0; j < inst->Instruction.NumSrcRegs; j++) { r600_bc_src(&alu.src[j], &ctx->src[j], i); } tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.chan = i; alu.dst.write = 1; alu.is_op3 = 1; if (i == lasti) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_dp(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, j, r; for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = ctx->inst_info->r600_opcode; for (j = 0; j < inst->Instruction.NumSrcRegs; j++) { r600_bc_src(&alu.src[j], &ctx->src[j], i); } tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.chan = i; alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; /* handle some special cases */ switch (ctx->inst_info->tgsi_opcode) { case TGSI_OPCODE_DP2: if (i > 1) { alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0; alu.src[0].chan = alu.src[1].chan = 0; } break; case TGSI_OPCODE_DP3: if (i > 2) { alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0; alu.src[0].chan = alu.src[1].chan = 0; } break; case TGSI_OPCODE_DPH: if (i == 3) { alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.src[0].neg = 0; } break; default: break; } if (i == 3) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_tex(struct r600_shader_ctx *ctx) { static float one_point_five = 1.5f; struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_tex tex; struct r600_bc_alu alu; unsigned src_gpr; int r, i; int opcode; /* Texture fetch instructions can only use gprs as source. * Also they cannot negate the source or take the absolute value */ const boolean src_requires_loading = (inst->Src[0].Register.File != TGSI_FILE_TEMPORARY && inst->Src[0].Register.File != TGSI_FILE_INPUT) || ctx->src[0].neg || ctx->src[0].abs; boolean src_loaded = FALSE; src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index; if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) { int out_chan; /* Add perspective divide */ if (ctx->bc->chiprev == CHIPREV_CAYMAN) { out_chan = 2; for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 3); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 2) alu.last = 1; if (out_chan == i) alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { out_chan = 3; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 3); alu.dst.sel = ctx->temp_reg; alu.dst.chan = out_chan; alu.last = 1; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = out_chan; r600_bc_src(&alu.src[1], &ctx->src[0], i); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 3; alu.last = 1; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; src_loaded = TRUE; src_gpr = ctx->temp_reg; } if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) { static const unsigned src0_swizzle[] = {2, 2, 0, 1}; static const unsigned src1_swizzle[] = {1, 0, 2, 2}; /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE); r600_bc_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]); r600_bc_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 3) alu.last = 1; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* tmp1.z = RCP_e(|tmp1.z|) */ if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 2; alu.src[0].abs = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 2) alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 2; alu.src[0].abs = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 2; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x * muladd has no writemask, have to use another temp */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.src[1].sel = ctx->temp_reg; alu.src[1].chan = 2; alu.src[2].sel = V_SQ_ALU_SRC_LITERAL; alu.src[2].chan = 0; alu.src[2].value = *(uint32_t *)&one_point_five; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 0; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 1; alu.src[1].sel = ctx->temp_reg; alu.src[1].chan = 2; alu.src[2].sel = V_SQ_ALU_SRC_LITERAL; alu.src[2].chan = 0; alu.src[2].value = *(uint32_t *)&one_point_five; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 1; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; src_loaded = TRUE; src_gpr = ctx->temp_reg; } if (src_requires_loading && !src_loaded) { for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); r600_bc_src(&alu.src[0], &ctx->src[0], i); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 3) alu.last = 1; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } src_loaded = TRUE; src_gpr = ctx->temp_reg; } opcode = ctx->inst_info->r600_opcode; if (opcode == SQ_TEX_INST_SAMPLE && (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)) opcode = SQ_TEX_INST_SAMPLE_C; memset(&tex, 0, sizeof(struct r600_bc_tex)); tex.inst = opcode; tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index; tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS; tex.src_gpr = src_gpr; tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index; tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; if (src_loaded) { tex.src_sel_x = 0; tex.src_sel_y = 1; tex.src_sel_z = 2; tex.src_sel_w = 3; } else { tex.src_sel_x = ctx->src[0].swizzle[0]; tex.src_sel_y = ctx->src[0].swizzle[1]; tex.src_sel_z = ctx->src[0].swizzle[2]; tex.src_sel_w = ctx->src[0].swizzle[3]; tex.src_rel = ctx->src[0].rel; } if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) { tex.src_sel_x = 1; tex.src_sel_y = 0; tex.src_sel_z = 3; tex.src_sel_w = 1; } if (inst->Texture.Texture != TGSI_TEXTURE_RECT) { tex.coord_type_x = 1; tex.coord_type_y = 1; tex.coord_type_z = 1; tex.coord_type_w = 1; } if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY) { tex.coord_type_z = 0; tex.src_sel_z = tex.src_sel_y; } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY) tex.coord_type_z = 0; if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D) tex.src_sel_w = tex.src_sel_z; r = r600_bc_add_tex(ctx->bc, &tex); if (r) return r; /* add shadow ambient support - gallium doesn't do it yet */ return 0; } static int tgsi_lrp(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); unsigned i; int r; /* optimize if it's just an equal balance */ if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) { for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD); r600_bc_src(&alu.src[0], &ctx->src[1], i); r600_bc_src(&alu.src[1], &ctx->src[2], i); alu.omod = 3; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.chan = i; if (i == lasti) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } /* 1 - src0 */ for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; r600_bc_src(&alu.src[1], &ctx->src[0], i); alu.src[1].neg = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == lasti) { alu.last = 1; } alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* (1 - src0) * src2 */ for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = i; r600_bc_src(&alu.src[1], &ctx->src[2], i); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == lasti) { alu.last = 1; } alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* src0 * src1 + (1 - src0) * src2 */ for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; r600_bc_src(&alu.src[0], &ctx->src[0], i); r600_bc_src(&alu.src[1], &ctx->src[1], i); alu.src[2].sel = ctx->temp_reg; alu.src[2].chan = i; tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.chan = i; if (i == lasti) { alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_cmp(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r; int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); for (i = 0; i < lasti + 1; i++) { if (!(inst->Dst[0].Register.WriteMask & (1 << i))) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE); r600_bc_src(&alu.src[0], &ctx->src[0], i); r600_bc_src(&alu.src[1], &ctx->src[2], i); r600_bc_src(&alu.src[2], &ctx->src[1], i); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.chan = i; alu.dst.write = 1; alu.is_op3 = 1; if (i == lasti) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int tgsi_xpd(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; static const unsigned int src0_swizzle[] = {2, 0, 1}; static const unsigned int src1_swizzle[] = {1, 2, 0}; struct r600_bc_alu alu; uint32_t use_temp = 0; int i, r; if (inst->Dst[0].Register.WriteMask != 0xf) use_temp = 1; for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); if (i < 3) { r600_bc_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]); r600_bc_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]); } else { alu.src[0].sel = V_SQ_ALU_SRC_0; alu.src[0].chan = i; alu.src[1].sel = V_SQ_ALU_SRC_0; alu.src[1].chan = i; } alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; alu.dst.write = 1; if (i == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); if (i < 3) { r600_bc_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]); r600_bc_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]); } else { alu.src[0].sel = V_SQ_ALU_SRC_0; alu.src[0].chan = i; alu.src[1].sel = V_SQ_ALU_SRC_0; alu.src[1].chan = i; } alu.src[2].sel = ctx->temp_reg; alu.src[2].neg = 1; alu.src[2].chan = i; if (use_temp) alu.dst.sel = ctx->temp_reg; else tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); alu.dst.chan = i; alu.dst.write = 1; alu.is_op3 = 1; if (i == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } if (use_temp) return tgsi_helper_copy(ctx, inst); return 0; } static int tgsi_exp(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int r; int i; /* result.x = 2^floor(src); */ if (inst->Dst[0].Register.WriteMask & 1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = 0; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 0) alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 0; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } /* result.y = tmp - floor(tmp); */ if ((inst->Dst[0].Register.WriteMask >> 1) & 1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; #if 0 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (r) return r; #endif alu.dst.write = 1; alu.dst.chan = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* result.z = RoughApprox2ToX(tmp);*/ if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) { if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 2) { alu.dst.write = 1; alu.last = 1; } r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.dst.chan = 2; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } /* result.w = 1.0;*/ if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 3; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return tgsi_helper_copy(ctx, inst); } static int tgsi_log(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int r; int i; /* result.x = floor(log2(src)); */ if (inst->Dst[0].Register.WriteMask & 1) { if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 0) alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = 0; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 0; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* result.y = src.x / (2 ^ floor(log2(src.x))); */ if ((inst->Dst[0].Register.WriteMask >> 1) & 1) { if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 1) alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.chan = 1; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 1; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 1) alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 1; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; if (i == 1) alu.dst.write = 1; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 1; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.src[1].sel = ctx->temp_reg; alu.src[1].chan = 1; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 1; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } /* result.z = log2(src);*/ if ((inst->Dst[0].Register.WriteMask >> 2) & 1) { if (ctx->bc->chiprev == CHIPREV_CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; if (i == 2) alu.dst.write = 1; alu.dst.chan = i; if (i == 2) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } else { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.dst.chan = 2; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } } /* result.w = 1.0; */ if ((inst->Dst[0].Register.WriteMask >> 3) & 1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.chan = 3; alu.dst.write = 1; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return tgsi_helper_copy(ctx, inst); } static int tgsi_eg_arl(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int r; memset(&alu, 0, sizeof(struct r600_bc_alu)); switch (inst->Instruction.Opcode) { case TGSI_OPCODE_ARL: alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR; break; case TGSI_OPCODE_ARR: alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT; break; default: assert(0); return -1; } r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.last = 1; alu.dst.sel = ctx->ar_reg; alu.dst.write = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; /* TODO: Note that the MOVA can be avoided if we never use AR for * indexing non-CB registers in the current ALU clause. Similarly, we * need to load AR from ar_reg again if we started a new clause * between ARL and AR usage. The easy way to do that is to remove * the MOVA here, and load it for the first AR access after ar_reg * has been modified in each clause. */ memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT; alu.src[0].sel = ctx->ar_reg; alu.src[0].chan = 0; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; return 0; } static int tgsi_r600_arl(struct r600_shader_ctx *ctx) { /* TODO from r600c, ar values don't persist between clauses */ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int r; switch (inst->Instruction.Opcode) { case TGSI_OPCODE_ARL: memset(&alu, 0, sizeof(alu)); alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR; r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->ar_reg; alu.dst.write = 1; alu.last = 1; if ((r = r600_bc_add_alu(ctx->bc, &alu))) return r; memset(&alu, 0, sizeof(alu)); alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT; alu.src[0].sel = ctx->ar_reg; alu.dst.sel = ctx->ar_reg; alu.dst.write = 1; alu.last = 1; if ((r = r600_bc_add_alu(ctx->bc, &alu))) return r; break; case TGSI_OPCODE_ARR: memset(&alu, 0, sizeof(alu)); alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT; r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.dst.sel = ctx->ar_reg; alu.dst.write = 1; alu.last = 1; if ((r = r600_bc_add_alu(ctx->bc, &alu))) return r; break; default: assert(0); return -1; } memset(&alu, 0, sizeof(alu)); alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT; alu.src[0].sel = ctx->ar_reg; alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; ctx->bc->cf_last->r6xx_uses_waterfall = 1; return 0; } static int tgsi_opdst(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; struct r600_bc_alu alu; int i, r = 0; for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (i == 0 || i == 3) { alu.src[0].sel = V_SQ_ALU_SRC_1; } else { r600_bc_src(&alu.src[0], &ctx->src[0], i); } if (i == 0 || i == 2) { alu.src[1].sel = V_SQ_ALU_SRC_1; } else { r600_bc_src(&alu.src[1], &ctx->src[1], i); } if (i == 3) alu.last = 1; r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; } return 0; } static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode) { struct r600_bc_alu alu; int r; memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = opcode; alu.predicate = 1; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; alu.dst.chan = 0; r600_bc_src(&alu.src[0], &ctx->src[0], 0); alu.src[1].sel = V_SQ_ALU_SRC_0; alu.src[1].chan = 0; alu.last = 1; r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)); if (r) return r; return 0; } static int pops(struct r600_shader_ctx *ctx, int pops) { int alu_pop = 3; if (ctx->bc->cf_last) { if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3) alu_pop = 0; else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3) alu_pop = 1; } alu_pop += pops; if (alu_pop == 1) { ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3; ctx->bc->force_add_cf = 1; } else if (alu_pop == 2) { ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3; ctx->bc->force_add_cf = 1; } else { r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP)); ctx->bc->cf_last->pop_count = pops; ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2; } return 0; } static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason) { switch(reason) { case FC_PUSH_VPM: ctx->bc->callstack[ctx->bc->call_sp].current--; break; case FC_PUSH_WQM: case FC_LOOP: ctx->bc->callstack[ctx->bc->call_sp].current -= 4; break; case FC_REP: /* TOODO : for 16 vp asic should -= 2; */ ctx->bc->callstack[ctx->bc->call_sp].current --; break; } } static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only) { if (check_max_only) { int diff; switch (reason) { case FC_PUSH_VPM: diff = 1; break; case FC_PUSH_WQM: diff = 4; break; default: assert(0); diff = 0; } if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) > ctx->bc->callstack[ctx->bc->call_sp].max) { ctx->bc->callstack[ctx->bc->call_sp].max = ctx->bc->callstack[ctx->bc->call_sp].current + diff; } return; } switch (reason) { case FC_PUSH_VPM: ctx->bc->callstack[ctx->bc->call_sp].current++; break; case FC_PUSH_WQM: case FC_LOOP: ctx->bc->callstack[ctx->bc->call_sp].current += 4; break; case FC_REP: ctx->bc->callstack[ctx->bc->call_sp].current++; break; } if ((ctx->bc->callstack[ctx->bc->call_sp].current) > ctx->bc->callstack[ctx->bc->call_sp].max) { ctx->bc->callstack[ctx->bc->call_sp].max = ctx->bc->callstack[ctx->bc->call_sp].current; } } static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp) { struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp]; sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid, sizeof(struct r600_bc_cf *) * (sp->num_mid + 1)); sp->mid[sp->num_mid] = ctx->bc->cf_last; sp->num_mid++; } static void fc_pushlevel(struct r600_shader_ctx *ctx, int type) { ctx->bc->fc_sp++; ctx->bc->fc_stack[ctx->bc->fc_sp].type = type; ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last; } static void fc_poplevel(struct r600_shader_ctx *ctx) { struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp]; if (sp->mid) { free(sp->mid); sp->mid = NULL; } sp->num_mid = 0; sp->start = NULL; sp->type = 0; ctx->bc->fc_sp--; } #if 0 static int emit_return(struct r600_shader_ctx *ctx) { r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN); return 0; } static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset) { r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP); ctx->bc->cf_last->pop_count = pops; /* TODO work out offset */ return 0; } static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value) { return 0; } static void emit_testflag(struct r600_shader_ctx *ctx) { } static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx) { emit_testflag(ctx); emit_jump_to_offset(ctx, 1, 4); emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0); pops(ctx, ifidx + 1); emit_return(ctx); } static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp) { emit_testflag(ctx); r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode); ctx->bc->cf_last->pop_count = 1; fc_set_mid(ctx, fc_sp); pops(ctx, 1); } #endif static int tgsi_if(struct r600_shader_ctx *ctx) { emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE)); r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP)); fc_pushlevel(ctx, FC_IF); callstack_check_depth(ctx, FC_PUSH_VPM, 0); return 0; } static int tgsi_else(struct r600_shader_ctx *ctx) { r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE)); ctx->bc->cf_last->pop_count = 1; fc_set_mid(ctx, ctx->bc->fc_sp); ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id; return 0; } static int tgsi_endif(struct r600_shader_ctx *ctx) { pops(ctx, 1); if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) { R600_ERR("if/endif unbalanced in shader\n"); return -1; } if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) { ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2; ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1; } else { ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2; } fc_poplevel(ctx); callstack_decrease_current(ctx, FC_PUSH_VPM); return 0; } static int tgsi_bgnloop(struct r600_shader_ctx *ctx) { r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL)); fc_pushlevel(ctx, FC_LOOP); /* check stack depth */ callstack_check_depth(ctx, FC_LOOP, 0); return 0; } static int tgsi_endloop(struct r600_shader_ctx *ctx) { int i; r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END)); if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) { R600_ERR("loop/endloop in shader code are not paired.\n"); return -EINVAL; } /* fixup loop pointers - from r600isa LOOP END points to CF after LOOP START, LOOP START point to CF after LOOP END BRK/CONT point to LOOP END CF */ ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2; ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2; for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) { ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id; } /* TODO add LOOPRET support */ fc_poplevel(ctx); callstack_decrease_current(ctx, FC_LOOP); return 0; } static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx) { unsigned int fscp; for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--) { if (FC_LOOP == ctx->bc->fc_stack[fscp].type) break; } if (fscp == 0) { R600_ERR("Break not inside loop/endloop pair\n"); return -EINVAL; } r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode); ctx->bc->cf_last->pop_count = 1; fc_set_mid(ctx, fscp); pops(ctx, 1); callstack_check_depth(ctx, FC_PUSH_VPM, 1); return 0; } static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl}, {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit}, /* FIXME: * For state trackers other than OpenGL, we'll want to use * _RECIP_IEEE instead. */ {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq}, {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp}, {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log}, {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2}, {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst}, {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2}, {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2}, {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap}, {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2}, {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3}, {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp}, {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2}, {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2}, {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow}, {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd}, /* gap */ {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig}, {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex}, {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex}, {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */ {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2}, {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2}, {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig}, {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap}, {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2}, {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl}, {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg}, {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp}, {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs}, {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont}, {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if}, /* gap */ {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else}, {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif}, /* gap */ {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2}, {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont}, {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop}, {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop}, {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */ {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */ /* gap */ {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, }; static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl}, {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit}, {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp}, {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log}, {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2}, {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst}, {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2}, {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2}, {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap}, {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2}, {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3}, {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp}, {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2}, {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2}, {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate}, {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow}, {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd}, /* gap */ {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig}, {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex}, {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex}, {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */ {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2}, {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2}, {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig}, {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap}, {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2}, {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl}, {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg}, {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp}, {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs}, {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont}, {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if}, /* gap */ {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else}, {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif}, /* gap */ {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2}, {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont}, {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop}, {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop}, {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */ {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */ /* gap */ {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, }; static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = { {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl}, {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit}, {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, cayman_emit_float_instr}, {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, cayman_emit_float_instr}, {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp}, {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log}, {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2}, {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst}, {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2}, {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2}, {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap}, {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2}, {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3}, {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp}, {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2}, {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2}, {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr}, {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr}, {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow}, {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd}, /* gap */ {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, cayman_trig}, {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex}, {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex}, {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */ {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2}, {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2}, {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, cayman_trig}, {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap}, {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2}, {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl}, {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg}, {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp}, {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs}, {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont}, {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if}, /* gap */ {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else}, {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif}, /* gap */ {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2}, {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont}, {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop}, {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop}, {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* gap */ {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */ {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */ /* gap */ {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, };