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/*
* Copyright 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef IRIS_RESOURCE_H
#define IRIS_RESOURCE_H
#include "pipe/p_state.h"
#include "util/u_inlines.h"
#include "intel/isl/isl.h"
struct iris_batch;
struct iris_context;
#define IRIS_MAX_MIPLEVELS 15
struct iris_format_info {
enum isl_format fmt;
struct isl_swizzle swizzle;
};
#define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
#define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
/**
* Resources represent a GPU buffer object or image (mipmap tree).
*
* They contain the storage (BO) and layout information (ISL surface).
*/
struct iris_resource {
struct pipe_resource base;
enum pipe_format internal_format;
/**
* The ISL surface layout information for this resource.
*
* This is not filled out for PIPE_BUFFER resources, but is guaranteed
* to be zeroed. Note that this also guarantees that res->surf.tiling
* will be ISL_TILING_LINEAR, so it's safe to check that.
*/
struct isl_surf surf;
/** Backing storage for the resource */
struct iris_bo *bo;
/**
* A bitfield of PIPE_BIND_* indicating how this resource was bound
* in the past. Only meaningful for PIPE_BUFFER; used for flushing.
*/
unsigned bind_history;
/**
* Auxiliary buffer information (CCS, MCS, or HiZ).
*/
struct {
/** The surface layout for the auxiliary buffer. */
struct isl_surf surf;
/** The buffer object containing the auxiliary data. */
struct iris_bo *bo;
/** Offset into 'bo' where the auxiliary surface starts. */
uint32_t offset;
/**
* \brief The type of auxiliary compression used by this resource.
*
* This describes the type of auxiliary compression that is intended to
* be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
* that auxiliary compression is permanently disabled. An aux usage
* other than ISL_AUX_USAGE_NONE does not imply that auxiliary
* compression will always be enabled for this surface.
*/
enum isl_aux_usage usage;
/**
* A bitfield of ISL_AUX_* modes that might this resource might use.
*
* For example, a surface might use both CCS_E and CCS_D at times.
*/
unsigned possible_usages;
/**
* \brief Maps miptree slices to their current aux state.
*
* This two-dimensional array is indexed as [level][layer] and stores an
* aux state for each slice.
*/
enum isl_aux_state **state;
} aux;
};
/**
* A simple <resource, offset> tuple for storing a reference to a
* piece of state stored in a GPU buffer object.
*/
struct iris_state_ref {
struct pipe_resource *res;
uint32_t offset;
};
/**
* Gallium CSO for sampler views (texture views).
*
* In addition to the normal pipe_resource, this adds an ISL view
* which may reinterpret the format or restrict levels/layers.
*
* These can also be linear texture buffers.
*/
struct iris_sampler_view {
struct pipe_sampler_view base;
struct isl_view view;
/* A short-cut (not a reference) to the actual resource being viewed.
* Multi-planar (or depth+stencil) images may have multiple resources
* chained together; this skips having to traverse base->texture->*.
*/
struct iris_resource *res;
/** The resource (BO) holding our SURFACE_STATE. */
struct iris_state_ref surface_state;
};
/**
* Gallium CSO for surfaces (framebuffer attachments).
*
* A view of a surface that can be bound to a color render target or
* depth/stencil attachment.
*/
struct iris_surface {
struct pipe_surface base;
struct isl_view view;
/** The resource (BO) holding our SURFACE_STATE. */
struct iris_state_ref surface_state;
};
/**
* Transfer object - information about a buffer mapping.
*/
struct iris_transfer {
struct pipe_transfer base;
struct pipe_debug_callback *dbg;
void *buffer;
void *ptr;
void (*unmap)(struct iris_transfer *);
};
/**
* Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
*/
static inline struct iris_bo *
iris_resource_bo(struct pipe_resource *p_res)
{
struct iris_resource *res = (void *) p_res;
return res->bo;
}
struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
enum pipe_format pf,
isl_surf_usage_flags_t usage);
struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
void iris_get_depth_stencil_resources(struct pipe_resource *res,
struct iris_resource **out_z,
struct iris_resource **out_s);
void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
void iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res);
#endif
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