1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
|
/*
* Copyright © 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/**
* @file iris_resource.c
*
* Resources are images, buffers, and other objects used by the GPU.
*
* XXX: explain resources
*/
#include <stdio.h>
#include <errno.h>
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "pipe/p_screen.h"
#include "util/os_memory.h"
#include "util/u_cpu_detect.h"
#include "util/u_inlines.h"
#include "util/u_format.h"
#include "util/u_transfer.h"
#include "util/u_transfer_helper.h"
#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
#include "iris_batch.h"
#include "iris_context.h"
#include "iris_resource.h"
#include "iris_screen.h"
#include "intel/common/gen_debug.h"
#include "isl/isl.h"
#include "drm-uapi/drm_fourcc.h"
#include "drm-uapi/i915_drm.h"
enum modifier_priority {
MODIFIER_PRIORITY_INVALID = 0,
MODIFIER_PRIORITY_LINEAR,
MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y,
MODIFIER_PRIORITY_Y_CCS,
};
static const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
[MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
};
static bool
modifier_is_supported(const struct gen_device_info *devinfo,
uint64_t modifier)
{
/* XXX: do something real */
switch (modifier) {
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_X_TILED:
case DRM_FORMAT_MOD_LINEAR:
return true;
case I915_FORMAT_MOD_Y_TILED_CCS:
case DRM_FORMAT_MOD_INVALID:
default:
return false;
}
}
static uint64_t
select_best_modifier(struct gen_device_info *devinfo,
const uint64_t *modifiers,
int count)
{
enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
for (int i = 0; i < count; i++) {
if (!modifier_is_supported(devinfo, modifiers[i]))
continue;
switch (modifiers[i]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
break;
case I915_FORMAT_MOD_Y_TILED:
prio = MAX2(prio, MODIFIER_PRIORITY_Y);
break;
case I915_FORMAT_MOD_X_TILED:
prio = MAX2(prio, MODIFIER_PRIORITY_X);
break;
case DRM_FORMAT_MOD_LINEAR:
prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
break;
case DRM_FORMAT_MOD_INVALID:
default:
break;
}
}
return priority_to_modifier[prio];
}
static enum isl_surf_dim
target_to_isl_surf_dim(enum pipe_texture_target target)
{
switch (target) {
case PIPE_BUFFER:
case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_1D_ARRAY:
return ISL_SURF_DIM_1D;
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_CUBE:
case PIPE_TEXTURE_RECT:
case PIPE_TEXTURE_2D_ARRAY:
case PIPE_TEXTURE_CUBE_ARRAY:
return ISL_SURF_DIM_2D;
case PIPE_TEXTURE_3D:
return ISL_SURF_DIM_3D;
case PIPE_MAX_TEXTURE_TYPES:
break;
}
unreachable("invalid texture type");
}
static isl_surf_usage_flags_t
pipe_bind_to_isl_usage(unsigned bindings)
{
isl_surf_usage_flags_t usage = 0;
if (bindings & PIPE_BIND_RENDER_TARGET)
usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
if (bindings & PIPE_BIND_SAMPLER_VIEW)
usage |= ISL_SURF_USAGE_TEXTURE_BIT;
if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
usage |= ISL_SURF_USAGE_STORAGE_BIT;
if (bindings & PIPE_BIND_DISPLAY_TARGET)
usage |= ISL_SURF_USAGE_DISPLAY_BIT;
return usage;
}
struct pipe_resource *
iris_resource_get_separate_stencil(struct pipe_resource *p_res)
{
/* For packed depth-stencil, we treat depth as the primary resource
* and store S8 as the "second plane" resource.
*/
return p_res->next;
}
static void
iris_resource_set_separate_stencil(struct pipe_resource *p_res,
struct pipe_resource *stencil)
{
assert(util_format_has_depth(util_format_description(p_res->format)));
pipe_resource_reference(&p_res->next, stencil);
}
void
iris_get_depth_stencil_resources(struct pipe_resource *res,
struct iris_resource **out_z,
struct iris_resource **out_s)
{
if (!res) {
*out_z = NULL;
*out_s = NULL;
return;
}
const struct util_format_description *desc =
util_format_description(res->format);
if (util_format_has_depth(desc)) {
*out_z = (void *) res;
*out_s = (void *) iris_resource_get_separate_stencil(res);
} else {
assert(util_format_has_stencil(desc));
*out_z = NULL;
*out_s = (void *) res;
}
}
static void
iris_resource_destroy(struct pipe_screen *screen,
struct pipe_resource *resource)
{
struct iris_resource *res = (struct iris_resource *)resource;
iris_bo_unreference(res->bo);
free(res);
}
static struct iris_resource *
iris_alloc_resource(struct pipe_screen *pscreen,
const struct pipe_resource *templ)
{
struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
if (!res)
return NULL;
res->base = *templ;
res->base.screen = pscreen;
pipe_reference_init(&res->base.reference, 1);
return res;
}
static struct pipe_resource *
iris_resource_create_for_buffer(struct pipe_screen *pscreen,
const struct pipe_resource *templ)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
assert(templ->target == PIPE_BUFFER);
assert(templ->height0 <= 1);
assert(templ->depth0 <= 1);
assert(templ->format == PIPE_FORMAT_NONE ||
util_format_get_blocksize(templ->format) == 1);
res->internal_format = templ->format;
res->surf.tiling = ISL_TILING_LINEAR;
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
memzone = IRIS_MEMZONE_SHADER;
name = "shader kernels";
} else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
memzone = IRIS_MEMZONE_SURFACE;
name = "surface state";
} else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
memzone = IRIS_MEMZONE_DYNAMIC;
name = "dynamic state";
}
res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
if (!res->bo) {
iris_resource_destroy(pscreen, &res->base);
return NULL;
}
return &res->base;
}
static struct pipe_resource *
iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
const struct pipe_resource *templ,
const uint64_t *modifiers,
int modifiers_count)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct gen_device_info *devinfo = &screen->devinfo;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
const struct util_format_description *format_desc =
util_format_description(templ->format);
if (!res)
return NULL;
const bool has_depth = util_format_has_depth(format_desc);
uint64_t modifier =
select_best_modifier(devinfo, modifiers, modifiers_count);
isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
if (modifier != DRM_FORMAT_MOD_INVALID) {
const struct isl_drm_modifier_info *mod_info =
isl_drm_modifier_get_info(modifier);
tiling_flags = 1 << mod_info->tiling;
} else {
if (modifiers_count > 0) {
fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
return NULL;
}
/* No modifiers - we can select our own tiling. */
if (has_depth) {
/* Depth must be Y-tiled */
tiling_flags = ISL_TILING_Y0_BIT;
} else if (templ->format == PIPE_FORMAT_S8_UINT) {
/* Stencil must be W-tiled */
tiling_flags = ISL_TILING_W_BIT;
} else if (templ->target == PIPE_BUFFER ||
templ->target == PIPE_TEXTURE_1D ||
templ->target == PIPE_TEXTURE_1D_ARRAY) {
/* Use linear for buffers and 1D textures */
tiling_flags = ISL_TILING_LINEAR_BIT;
}
/* Use linear for staging buffers */
if (templ->usage == PIPE_USAGE_STAGING ||
templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
tiling_flags = ISL_TILING_LINEAR_BIT;
}
isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
if (templ->target == PIPE_TEXTURE_CUBE ||
templ->target == PIPE_TEXTURE_CUBE_ARRAY)
usage |= ISL_SURF_USAGE_CUBE_BIT;
if (templ->usage != PIPE_USAGE_STAGING) {
if (templ->format == PIPE_FORMAT_S8_UINT)
usage |= ISL_SURF_USAGE_STENCIL_BIT;
else if (has_depth)
usage |= ISL_SURF_USAGE_DEPTH_BIT;
}
enum pipe_format pfmt = templ->format;
res->internal_format = pfmt;
/* Should be handled by u_transfer_helper */
assert(!util_format_is_depth_and_stencil(pfmt));
struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
UNUSED const bool isl_surf_created_successfully =
isl_surf_init(&screen->isl_dev, &res->surf,
.dim = target_to_isl_surf_dim(templ->target),
.format = fmt.fmt,
.width = templ->width0,
.height = templ->height0,
.depth = templ->depth0,
.levels = templ->last_level + 1,
.array_len = templ->array_size,
.samples = MAX2(templ->nr_samples, 1),
.min_alignment_B = 0,
.row_pitch_B = 0,
.usage = usage,
.tiling_flags = tiling_flags);
assert(isl_surf_created_successfully);
const char *name = "miptree";
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
/* These are for u_upload_mgr buffers only */
assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B,
memzone,
isl_tiling_to_i915_tiling(res->surf.tiling),
res->surf.row_pitch_B, 0);
if (!res->bo) {
iris_resource_destroy(pscreen, &res->base);
return NULL;
}
return &res->base;
}
static struct pipe_resource *
iris_resource_create(struct pipe_screen *pscreen,
const struct pipe_resource *templ)
{
if (templ->target == PIPE_BUFFER)
return iris_resource_create_for_buffer(pscreen, templ);
else
return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
}
static uint64_t
tiling_to_modifier(uint32_t tiling)
{
static const uint64_t map[] = {
[I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
[I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
[I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
};
assert(tiling < ARRAY_SIZE(map));
return map[tiling];
}
static struct pipe_resource *
iris_resource_from_user_memory(struct pipe_screen *pscreen,
const struct pipe_resource *templ,
void *user_memory)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct iris_bufmgr *bufmgr = screen->bufmgr;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
if (!res)
return NULL;
assert(templ->target == PIPE_BUFFER);
res->internal_format = templ->format;
res->bo = iris_bo_create_userptr(bufmgr, "user",
user_memory, templ->width0,
IRIS_MEMZONE_OTHER);
if (!res->bo) {
free(res);
return NULL;
}
return &res->base;
}
static struct pipe_resource *
iris_resource_from_handle(struct pipe_screen *pscreen,
const struct pipe_resource *templ,
struct winsys_handle *whandle,
unsigned usage)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct gen_device_info *devinfo = &screen->devinfo;
struct iris_bufmgr *bufmgr = screen->bufmgr;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
if (!res)
return NULL;
if (whandle->offset != 0) {
dbg_printf("Attempt to import unsupported winsys offset %u\n",
whandle->offset);
goto fail;
}
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_FD:
res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle);
break;
case WINSYS_HANDLE_TYPE_SHARED:
res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
whandle->handle);
break;
default:
unreachable("invalid winsys handle type");
}
if (!res->bo)
return NULL;
uint64_t modifier = whandle->modifier;
if (modifier == DRM_FORMAT_MOD_INVALID) {
modifier = tiling_to_modifier(res->bo->tiling_mode);
}
const struct isl_drm_modifier_info *mod_info =
isl_drm_modifier_get_info(modifier);
assert(mod_info);
isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
const struct iris_format_info fmt =
iris_format_for_usage(devinfo, templ->format, isl_usage);
if (templ->target == PIPE_BUFFER) {
res->surf.tiling = ISL_TILING_LINEAR;
} else {
isl_surf_init(&screen->isl_dev, &res->surf,
.dim = target_to_isl_surf_dim(templ->target),
.format = fmt.fmt,
.width = templ->width0,
.height = templ->height0,
.depth = templ->depth0,
.levels = templ->last_level + 1,
.array_len = templ->array_size,
.samples = MAX2(templ->nr_samples, 1),
.min_alignment_B = 0,
.row_pitch_B = whandle->stride,
.usage = isl_usage,
.tiling_flags = 1 << mod_info->tiling);
assert(res->bo->tiling_mode ==
isl_tiling_to_i915_tiling(res->surf.tiling));
}
return &res->base;
fail:
iris_resource_destroy(pscreen, &res->base);
return NULL;
}
static boolean
iris_resource_get_handle(struct pipe_screen *pscreen,
struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *whandle,
unsigned usage)
{
struct iris_resource *res = (struct iris_resource *)resource;
/* If this is a buffer, stride should be 0 - no need to special case */
whandle->stride = res->surf.row_pitch_B;
whandle->modifier = tiling_to_modifier(res->bo->tiling_mode);
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_SHARED:
return iris_bo_flink(res->bo, &whandle->handle) == 0;
case WINSYS_HANDLE_TYPE_KMS:
whandle->handle = iris_bo_export_gem_handle(res->bo);
return true;
case WINSYS_HANDLE_TYPE_FD:
return iris_bo_export_dmabuf(res->bo, (int *) &whandle->handle) == 0;
}
return false;
}
static void
get_image_offset_el(struct isl_surf *surf, unsigned level, unsigned z,
unsigned *out_x0_el, unsigned *out_y0_el)
{
if (surf->dim == ISL_SURF_DIM_3D) {
isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
} else {
isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
}
}
/**
* Get pointer offset into stencil buffer.
*
* The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
* must decode the tile's layout in software.
*
* See
* - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
* Format.
* - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
*
* Even though the returned offset is always positive, the return type is
* signed due to
* commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
* mesa: Fix return type of _mesa_get_format_bytes() (#37351)
*/
static intptr_t
s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
{
uint32_t tile_size = 4096;
uint32_t tile_width = 64;
uint32_t tile_height = 64;
uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
uint32_t tile_x = x / tile_width;
uint32_t tile_y = y / tile_height;
/* The byte's address relative to the tile's base addres. */
uint32_t byte_x = x % tile_width;
uint32_t byte_y = y % tile_height;
uintptr_t u = tile_y * row_size
+ tile_x * tile_size
+ 512 * (byte_x / 8)
+ 64 * (byte_y / 8)
+ 32 * ((byte_y / 4) % 2)
+ 16 * ((byte_x / 4) % 2)
+ 8 * ((byte_y / 2) % 2)
+ 4 * ((byte_x / 2) % 2)
+ 2 * (byte_y % 2)
+ 1 * (byte_x % 2);
if (swizzled) {
/* adjust for bit6 swizzling */
if (((byte_x / 8) % 2) == 1) {
if (((byte_y / 8) % 2) == 0) {
u += 64;
} else {
u -= 64;
}
}
}
return u;
}
static void
iris_unmap_s8(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
const bool has_swizzling = false;
if (xfer->usage & PIPE_TRANSFER_WRITE) {
uint8_t *untiled_s8_map = map->ptr;
uint8_t *tiled_s8_map =
iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW);
struct pipe_box box = xfer->box;
for (int s = 0; s < box.depth; s++) {
unsigned x0_el, y0_el;
get_image_offset_el(surf, xfer->level, box.z, &x0_el, &y0_el);
for (uint32_t y = 0; y < box.height; y++) {
for (uint32_t x = 0; x < box.width; x++) {
ptrdiff_t offset = s8_offset(surf->row_pitch_B,
x0_el + box.x + x,
y0_el + box.y + y,
has_swizzling);
tiled_s8_map[offset] =
untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
}
}
box.z++;
}
}
free(map->buffer);
}
static void
iris_map_s8(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
xfer->stride = surf->row_pitch_B;
xfer->layer_stride = xfer->stride * xfer->box.height;
/* The tiling and detiling functions require that the linear buffer has
* a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
* over-allocate the linear buffer to get the proper alignment.
*/
map->buffer = map->ptr = malloc(xfer->layer_stride * xfer->box.depth);
assert(map->buffer);
const bool has_swizzling = false;
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* invalidate is set, since we'll be writing the whole rectangle from our
* temporary buffer back out.
*/
if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
uint8_t *untiled_s8_map = map->ptr;
uint8_t *tiled_s8_map =
iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW);
struct pipe_box box = xfer->box;
for (int s = 0; s < box.depth; s++) {
unsigned x0_el, y0_el;
get_image_offset_el(surf, xfer->level, box.z, &x0_el, &y0_el);
for (uint32_t y = 0; y < box.height; y++) {
for (uint32_t x = 0; x < box.width; x++) {
ptrdiff_t offset = s8_offset(surf->row_pitch_B,
x0_el + box.x + x,
y0_el + box.y + y,
has_swizzling);
untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
tiled_s8_map[offset];
}
}
box.z++;
}
}
map->unmap = iris_unmap_s8;
}
/* Compute extent parameters for use with tiled_memcpy functions.
* xs are in units of bytes and ys are in units of strides.
*/
static inline void
tile_extents(struct isl_surf *surf,
const struct pipe_box *box,
unsigned level,
unsigned *x1_B, unsigned *x2_B,
unsigned *y1_el, unsigned *y2_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
const unsigned cpp = fmtl->bpb / 8;
assert(box->x % fmtl->bw == 0);
assert(box->y % fmtl->bh == 0);
unsigned x0_el, y0_el;
get_image_offset_el(surf, level, box->z, &x0_el, &y0_el);
*x1_B = (box->x / fmtl->bw + x0_el) * cpp;
*y1_el = box->y / fmtl->bh + y0_el;
*x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
*y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
}
static void
iris_unmap_tiled_memcpy(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_box box = xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
const bool has_swizzling = false;
if (xfer->usage & PIPE_TRANSFER_WRITE) {
char *dst = iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW);
for (int s = 0; s < box.depth; s++) {
unsigned x1, x2, y1, y2;
tile_extents(surf, &box, xfer->level, &x1, &x2, &y1, &y2);
void *ptr = map->ptr + s * xfer->layer_stride;
isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
surf->row_pitch_B, xfer->stride,
has_swizzling, surf->tiling, ISL_MEMCPY);
box.z++;
}
}
os_free_aligned(map->buffer);
map->buffer = map->ptr = NULL;
}
static void
iris_map_tiled_memcpy(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
xfer->stride = ALIGN(surf->row_pitch_B, 16);
xfer->layer_stride = xfer->stride * xfer->box.height;
unsigned x1, x2, y1, y2;
tile_extents(surf, &xfer->box, xfer->level, &x1, &x2, &y1, &y2);
/* The tiling and detiling functions require that the linear buffer has
* a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
* over-allocate the linear buffer to get the proper alignment.
*/
map->buffer =
os_malloc_aligned(xfer->layer_stride * xfer->box.depth, 16);
assert(map->buffer);
map->ptr = (char *)map->buffer + (x1 & 0xf);
const bool has_swizzling = false;
// XXX: PIPE_TRANSFER_READ?
if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
char *src = iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW);
struct pipe_box box = xfer->box;
for (int s = 0; s < box.depth; s++) {
unsigned x1, x2, y1, y2;
tile_extents(surf, &box, xfer->level, &x1, &x2, &y1, &y2);
/* Use 's' rather than 'box.z' to rebase the first slice to 0. */
void *ptr = map->ptr + s * xfer->layer_stride;
isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
surf->row_pitch_B, has_swizzling,
surf->tiling, ISL_MEMCPY);
box.z++;
}
}
map->unmap = iris_unmap_tiled_memcpy;
}
static void
iris_map_direct(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage);
if (res->base.target == PIPE_BUFFER) {
xfer->stride = 0;
xfer->layer_stride = 0;
map->ptr = ptr + box->x;
} else {
struct isl_surf *surf = &res->surf;
const struct isl_format_layout *fmtl =
isl_format_get_layout(surf->format);
const unsigned cpp = fmtl->bpb / 8;
unsigned x0_el, y0_el;
get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
xfer->stride = isl_surf_get_row_pitch_B(surf);
xfer->layer_stride = isl_surf_get_array_pitch(surf);
map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
}
}
static void *
iris_transfer_map(struct pipe_context *ctx,
struct pipe_resource *resource,
unsigned level,
enum pipe_transfer_usage usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
{
struct iris_context *ice = (struct iris_context *)ctx;
struct iris_resource *res = (struct iris_resource *)resource;
struct isl_surf *surf = &res->surf;
if (surf->tiling != ISL_TILING_LINEAR &&
(usage & PIPE_TRANSFER_MAP_DIRECTLY))
return NULL;
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
if (iris_batch_references(&ice->batches[i], res->bo))
iris_batch_flush(&ice->batches[i]);
}
}
if ((usage & PIPE_TRANSFER_DONTBLOCK) && iris_bo_busy(res->bo))
return NULL;
struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
struct pipe_transfer *xfer = &map->base;
// PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
// PIPE_TRANSFER_DISCARD_RANGE
if (!map)
return NULL;
memset(map, 0, sizeof(*map));
map->dbg = &ice->dbg;
pipe_resource_reference(&xfer->resource, resource);
xfer->level = level;
xfer->usage = usage;
xfer->box = *box;
*ptransfer = xfer;
xfer->usage &= (PIPE_TRANSFER_READ |
PIPE_TRANSFER_WRITE |
PIPE_TRANSFER_UNSYNCHRONIZED |
PIPE_TRANSFER_PERSISTENT |
PIPE_TRANSFER_COHERENT |
PIPE_TRANSFER_DISCARD_RANGE);
if (surf->tiling == ISL_TILING_W) {
// XXX: just teach iris_map_tiled_memcpy about W tiling...
iris_map_s8(map);
} else if (surf->tiling != ISL_TILING_LINEAR) {
iris_map_tiled_memcpy(map);
} else {
iris_map_direct(map);
}
return map->ptr;
}
static void
iris_transfer_flush_region(struct pipe_context *ctx,
struct pipe_transfer *xfer,
const struct pipe_box *box)
{
struct iris_context *ice = (struct iris_context *)ctx;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
// XXX: don't emit flushes in both engines...? we may also need to flush
// even if there isn't a draw yet - may still be stale data in caches...
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
if (ice->batches[i].contains_draw) {
iris_batch_maybe_flush(&ice->batches[i], 24);
iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
}
}
}
static void
iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
{
struct iris_context *ice = (struct iris_context *)ctx;
struct iris_transfer *map = (void *) xfer;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
if (map->unmap)
map->unmap(map);
// XXX: don't emit flushes in both engines...?
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
if (ice->batches[i].contains_draw) {
iris_batch_maybe_flush(&ice->batches[i], 24);
iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
}
}
pipe_resource_reference(&xfer->resource, NULL);
slab_free(&ice->transfer_pool, map);
}
static void
iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
{
}
void
iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res)
{
if (res->base.target != PIPE_BUFFER)
return;
unsigned flush = PIPE_CONTROL_CS_STALL;
uint64_t dirty = 0ull;
if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
dirty |= IRIS_DIRTY_CONSTANTS_VS |
IRIS_DIRTY_CONSTANTS_TCS |
IRIS_DIRTY_CONSTANTS_TES |
IRIS_DIRTY_CONSTANTS_GS |
IRIS_DIRTY_CONSTANTS_FS |
IRIS_DIRTY_CONSTANTS_CS |
IRIS_ALL_DIRTY_BINDINGS;
}
if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
iris_emit_pipe_control_flush(batch, flush);
ice->state.dirty |= dirty;
}
static enum pipe_format
iris_resource_get_internal_format(struct pipe_resource *p_res)
{
struct iris_resource *res = (void *) p_res;
return res->internal_format;
}
static const struct u_transfer_vtbl transfer_vtbl = {
.resource_create = iris_resource_create,
.resource_destroy = iris_resource_destroy,
.transfer_map = iris_transfer_map,
.transfer_unmap = iris_transfer_unmap,
.transfer_flush_region = iris_transfer_flush_region,
.get_internal_format = iris_resource_get_internal_format,
.set_stencil = iris_resource_set_separate_stencil,
.get_stencil = iris_resource_get_separate_stencil,
};
void
iris_init_screen_resource_functions(struct pipe_screen *pscreen)
{
pscreen->resource_create_with_modifiers =
iris_resource_create_with_modifiers;
pscreen->resource_create = u_transfer_helper_resource_create;
pscreen->resource_from_user_memory = iris_resource_from_user_memory;
pscreen->resource_from_handle = iris_resource_from_handle;
pscreen->resource_get_handle = iris_resource_get_handle;
pscreen->resource_destroy = u_transfer_helper_resource_destroy;
pscreen->transfer_helper =
u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
}
void
iris_init_resource_functions(struct pipe_context *ctx)
{
ctx->flush_resource = iris_flush_resource;
ctx->transfer_map = u_transfer_helper_transfer_map;
ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
ctx->buffer_subdata = u_default_buffer_subdata;
ctx->texture_subdata = u_default_texture_subdata;
}
|