1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
|
/*
* Mesa 3-D graphics library
*
* Copyright (C) 2012-2013 LunarG, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Chia-I Wu <olv@lunarg.com>
*/
#include "util/u_surface.h"
#include "util/u_transfer.h"
#include "ilo_cp.h"
#include "ilo_context.h"
#include "ilo_screen.h"
#include "ilo_resource.h"
/* use PIPE_BIND_CUSTOM to indicate MCS */
#define ILO_BIND_MCS PIPE_BIND_CUSTOM
enum ilo_transfer_map_method {
ILO_TRANSFER_MAP_DIRECT,
ILO_TRANSFER_MAP_STAGING_SYS,
};
struct ilo_transfer {
struct pipe_transfer base;
enum ilo_transfer_map_method method;
void *ptr;
void *staging_sys;
};
static inline struct ilo_transfer *
ilo_transfer(struct pipe_transfer *transfer)
{
return (struct ilo_transfer *) transfer;
}
static struct intel_bo *
alloc_buf_bo(const struct ilo_resource *res)
{
struct ilo_screen *is = ilo_screen(res->base.screen);
struct intel_bo *bo;
const char *name;
const unsigned size = res->bo_width;
switch (res->base.bind) {
case PIPE_BIND_VERTEX_BUFFER:
name = "vertex buffer";
break;
case PIPE_BIND_INDEX_BUFFER:
name = "index buffer";
break;
case PIPE_BIND_CONSTANT_BUFFER:
name = "constant buffer";
break;
case PIPE_BIND_STREAM_OUTPUT:
name = "stream output";
break;
default:
name = "unknown buffer";
break;
}
/* this is what a buffer supposed to be like */
assert(res->bo_width * res->bo_height * res->bo_cpp == size);
assert(res->tiling == INTEL_TILING_NONE);
assert(res->bo_stride == 0);
if (res->handle) {
bo = is->winsys->import_handle(is->winsys, name,
res->bo_width, res->bo_height, res->bo_cpp, res->handle);
/* since the bo is shared to us, make sure it meets the expectations */
if (bo) {
assert(bo->get_size(res->bo) == size);
assert(bo->get_tiling(res->bo) == res->tiling);
assert(bo->get_pitch(res->bo) == res->bo_stride);
}
}
else {
bo = is->winsys->alloc_buffer(is->winsys, name, size, 0);
}
return bo;
}
static struct intel_bo *
alloc_tex_bo(const struct ilo_resource *res)
{
struct ilo_screen *is = ilo_screen(res->base.screen);
struct intel_bo *bo;
const char *name;
switch (res->base.target) {
case PIPE_TEXTURE_1D:
name = "1D texture";
break;
case PIPE_TEXTURE_2D:
name = "2D texture";
break;
case PIPE_TEXTURE_3D:
name = "3D texture";
break;
case PIPE_TEXTURE_CUBE:
name = "cube texture";
break;
case PIPE_TEXTURE_RECT:
name = "rectangle texture";
break;
case PIPE_TEXTURE_1D_ARRAY:
name = "1D array texture";
break;
case PIPE_TEXTURE_2D_ARRAY:
name = "2D array texture";
break;
case PIPE_TEXTURE_CUBE_ARRAY:
name = "cube array texture";
break;
default:
name ="unknown texture";
break;
}
if (res->handle) {
bo = is->winsys->import_handle(is->winsys, name,
res->bo_width, res->bo_height, res->bo_cpp, res->handle);
}
else {
const bool for_render =
(res->base.bind & (PIPE_BIND_DEPTH_STENCIL |
PIPE_BIND_RENDER_TARGET));
const unsigned long flags =
(for_render) ? INTEL_ALLOC_FOR_RENDER : 0;
bo = is->winsys->alloc(is->winsys, name,
res->bo_width, res->bo_height, res->bo_cpp,
res->tiling, flags);
}
return bo;
}
static bool
realloc_bo(struct ilo_resource *res)
{
struct intel_bo *old_bo = res->bo;
/* a shared bo cannot be reallocated */
if (old_bo && res->handle)
return false;
if (res->base.target == PIPE_BUFFER)
res->bo = alloc_buf_bo(res);
else
res->bo = alloc_tex_bo(res);
if (!res->bo) {
res->bo = old_bo;
return false;
}
/* winsys may decide to use a different tiling */
res->tiling = res->bo->get_tiling(res->bo);
res->bo_stride = res->bo->get_pitch(res->bo);
if (old_bo)
old_bo->unreference(old_bo);
return true;
}
static void
ilo_transfer_inline_write(struct pipe_context *pipe,
struct pipe_resource *r,
unsigned level,
unsigned usage,
const struct pipe_box *box,
const void *data,
unsigned stride,
unsigned layer_stride)
{
struct ilo_context *ilo = ilo_context(pipe);
struct ilo_resource *res = ilo_resource(r);
int offset, size;
bool will_be_busy;
/*
* Fall back to map(), memcpy(), and unmap(). We use this path for
* unsynchronized write, as the buffer is likely to be busy and pwrite()
* will stall.
*/
if (unlikely(res->base.target != PIPE_BUFFER) ||
(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
u_default_transfer_inline_write(pipe, r,
level, usage, box, data, stride, layer_stride);
return;
}
/*
* XXX With hardware context support, the bo may be needed by GPU without
* being referenced by ilo->cp->bo. We have to flush unconditionally, and
* that is bad.
*/
if (ilo->cp->hw_ctx)
ilo_cp_flush(ilo->cp);
will_be_busy = ilo->cp->bo->references(ilo->cp->bo, res->bo);
/* see if we can avoid stalling */
if (will_be_busy || intel_bo_is_busy(res->bo)) {
bool will_stall = true;
if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
/* old data not needed so discard the old bo to avoid stalling */
if (realloc_bo(res))
will_stall = false;
}
else {
/*
* We could allocate a temporary bo to hold the data and emit
* pipelined copy blit to move them to res->bo. But for now, do
* nothing.
*/
}
/* flush to make bo busy (so that pwrite() stalls as it should be) */
if (will_stall && will_be_busy)
ilo_cp_flush(ilo->cp);
}
/* for PIPE_BUFFERs, conversion should not be needed */
assert(res->bo_format == res->base.format);
/* they should specify just an offset and a size */
assert(level == 0);
assert(box->y == 0);
assert(box->z == 0);
assert(box->height == 1);
assert(box->depth == 1);
offset = box->x;
size = box->width;
res->bo->pwrite(res->bo, offset, size, data);
}
static void
transfer_unmap_sys(struct ilo_context *ilo,
struct ilo_resource *res,
struct ilo_transfer *xfer)
{
const void *src = xfer->ptr;
struct pipe_transfer *dst_xfer;
void *dst;
dst = ilo->base.transfer_map(&ilo->base,
xfer->base.resource, xfer->base.level,
PIPE_TRANSFER_WRITE |
PIPE_TRANSFER_MAP_DIRECTLY |
PIPE_TRANSFER_DISCARD_RANGE,
&xfer->base.box, &dst_xfer);
if (!dst_xfer) {
ilo_err("failed to map resource for moving staging data\n");
FREE(xfer->staging_sys);
return;
}
util_copy_box(dst, res->bo_format,
dst_xfer->stride, dst_xfer->layer_stride, 0, 0, 0,
dst_xfer->box.width, dst_xfer->box.height, dst_xfer->box.depth,
src, xfer->base.stride, xfer->base.layer_stride, 0, 0, 0);
ilo->base.transfer_unmap(&ilo->base, dst_xfer);
FREE(xfer->staging_sys);
}
static bool
transfer_map_sys(struct ilo_context *ilo,
struct ilo_resource *res,
struct ilo_transfer *xfer)
{
const struct pipe_box *box = &xfer->base.box;
const size_t stride = util_format_get_stride(res->base.format, box->width);
const size_t size =
util_format_get_2d_size(res->base.format, stride, box->height);
bool read_back;
if (xfer->base.usage & PIPE_TRANSFER_READ) {
read_back = true;
}
else if (xfer->base.usage & PIPE_TRANSFER_WRITE) {
const unsigned discard_flags =
(PIPE_TRANSFER_DISCARD_RANGE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE);
if (!(xfer->base.usage & discard_flags))
read_back = true;
}
/* TODO */
if (read_back)
return false;
xfer->staging_sys = MALLOC(size * box->depth);
if (!xfer->staging_sys)
return false;
xfer->base.stride = stride;
xfer->base.layer_stride = size;
xfer->ptr = xfer->staging_sys;
return true;
}
static void
transfer_unmap_direct(struct ilo_context *ilo,
struct ilo_resource *res,
struct ilo_transfer *xfer)
{
res->bo->unmap(res->bo);
}
static bool
transfer_map_direct(struct ilo_context *ilo,
struct ilo_resource *res,
struct ilo_transfer *xfer)
{
int x, y, err;
if (xfer->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED)
err = res->bo->map_unsynchronized(res->bo);
/* prefer map() when there is the last-level cache */
else if (res->tiling == INTEL_TILING_NONE &&
(ilo->dev->has_llc || (xfer->base.usage & PIPE_TRANSFER_READ)))
err = res->bo->map(res->bo, (xfer->base.usage & PIPE_TRANSFER_WRITE));
else
err = res->bo->map_gtt(res->bo);
if (err)
return false;
/* note that stride is for a block row, not a texel row */
xfer->base.stride = res->bo_stride;
/*
* we can walk through layers when the resource is a texture array or
* when this is the first level of a 3D texture being mapped
*/
if (res->base.array_size > 1 ||
(res->base.target == PIPE_TEXTURE_3D && xfer->base.level == 0)) {
const unsigned qpitch = res->slice_offsets[xfer->base.level][1].y -
res->slice_offsets[xfer->base.level][0].y;
assert(qpitch % res->block_height == 0);
xfer->base.layer_stride = (qpitch / res->block_height) * xfer->base.stride;
}
else {
xfer->base.layer_stride = 0;
}
x = res->slice_offsets[xfer->base.level][xfer->base.box.z].x;
y = res->slice_offsets[xfer->base.level][xfer->base.box.z].y;
x += xfer->base.box.x;
y += xfer->base.box.y;
/* in blocks */
assert(x % res->block_width == 0 && y % res->block_height == 0);
x /= res->block_width;
y /= res->block_height;
xfer->ptr = res->bo->get_virtual(res->bo);
xfer->ptr += y * res->bo_stride + x * res->bo_cpp;
return true;
}
/**
* Choose the best mapping method, depending on the transfer usage and whether
* the bo is busy.
*/
static bool
transfer_map_choose_method(struct ilo_context *ilo,
struct ilo_resource *res,
struct ilo_transfer *xfer)
{
bool will_be_busy, will_stall;
xfer->method = ILO_TRANSFER_MAP_DIRECT;
/* unsynchronized map does not stall */
if (xfer->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED)
return true;
will_be_busy = ilo->cp->bo->references(ilo->cp->bo, res->bo);
if (!will_be_busy) {
/*
* XXX With hardware context support, the bo may be needed by GPU
* without being referenced by ilo->cp->bo. We have to flush
* unconditionally, and that is bad.
*/
if (ilo->cp->hw_ctx)
ilo_cp_flush(ilo->cp);
if (!intel_bo_is_busy(res->bo))
return true;
}
/* bo is busy and mapping it will stall */
will_stall = true;
if (xfer->base.usage & PIPE_TRANSFER_MAP_DIRECTLY) {
/* nothing we can do */
}
else if (xfer->base.usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
/* discard old bo and allocate a new one for mapping */
if (realloc_bo(res))
will_stall = false;
}
else if (xfer->base.usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
/*
* We could allocate and return a system buffer here. When a region of
* the buffer is explicitly flushed, we pwrite() the region to a
* temporary bo and emit pipelined copy blit.
*
* For now, do nothing.
*/
}
else if (xfer->base.usage & PIPE_TRANSFER_DISCARD_RANGE) {
/*
* We could allocate a temporary bo for mapping, and emit pipelined copy
* blit upon unmapping.
*
* For now, do nothing.
*/
}
if (will_stall) {
if (xfer->base.usage & PIPE_TRANSFER_DONTBLOCK)
return false;
/* flush to make bo busy (so that map() stalls as it should be) */
if (will_be_busy)
ilo_cp_flush(ilo->cp);
}
return true;
}
static void
ilo_transfer_flush_region(struct pipe_context *pipe,
struct pipe_transfer *transfer,
const struct pipe_box *box)
{
}
static void
ilo_transfer_unmap(struct pipe_context *pipe,
struct pipe_transfer *transfer)
{
struct ilo_context *ilo = ilo_context(pipe);
struct ilo_resource *res = ilo_resource(transfer->resource);
struct ilo_transfer *xfer = ilo_transfer(transfer);
switch (xfer->method) {
case ILO_TRANSFER_MAP_DIRECT:
transfer_unmap_direct(ilo, res, xfer);
break;
case ILO_TRANSFER_MAP_STAGING_SYS:
transfer_unmap_sys(ilo, res, xfer);
break;
default:
assert(!"unknown mapping method");
break;
}
pipe_resource_reference(&xfer->base.resource, NULL);
FREE(xfer);
}
static void *
ilo_transfer_map(struct pipe_context *pipe,
struct pipe_resource *r,
unsigned level,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **transfer)
{
struct ilo_context *ilo = ilo_context(pipe);
struct ilo_resource *res = ilo_resource(r);
struct ilo_transfer *xfer;
int ok;
xfer = MALLOC_STRUCT(ilo_transfer);
if (!xfer) {
*transfer = NULL;
return NULL;
}
xfer->base.resource = NULL;
pipe_resource_reference(&xfer->base.resource, &res->base);
xfer->base.level = level;
xfer->base.usage = usage;
xfer->base.box = *box;
ok = transfer_map_choose_method(ilo, res, xfer);
if (ok) {
switch (xfer->method) {
case ILO_TRANSFER_MAP_DIRECT:
ok = transfer_map_direct(ilo, res, xfer);
break;
case ILO_TRANSFER_MAP_STAGING_SYS:
ok = transfer_map_sys(ilo, res, xfer);
break;
default:
assert(!"unknown mapping method");
ok = false;
break;
}
}
if (!ok) {
pipe_resource_reference(&xfer->base.resource, NULL);
FREE(xfer);
*transfer = NULL;
return NULL;
}
*transfer = &xfer->base;
return xfer->ptr;
}
static bool
alloc_slice_offsets(struct ilo_resource *res)
{
int depth, lv;
/* sum the depths of all levels */
depth = 0;
for (lv = 0; lv <= res->base.last_level; lv++)
depth += u_minify(res->base.depth0, lv);
/*
* There are (depth * res->base.array_size) slices. Either depth is one
* (non-3D) or res->base.array_size is one (non-array), but it does not
* matter.
*/
res->slice_offsets[0] =
CALLOC(depth * res->base.array_size, sizeof(res->slice_offsets[0][0]));
if (!res->slice_offsets[0])
return false;
/* point to the respective positions in the buffer */
for (lv = 1; lv <= res->base.last_level; lv++) {
res->slice_offsets[lv] = res->slice_offsets[lv - 1] +
u_minify(res->base.depth0, lv - 1) * res->base.array_size;
}
return true;
}
static void
free_slice_offsets(struct ilo_resource *res)
{
int lv;
FREE(res->slice_offsets[0]);
for (lv = 0; lv <= res->base.last_level; lv++)
res->slice_offsets[lv] = NULL;
}
struct layout_tex_info {
bool compressed;
int block_width, block_height;
int align_i, align_j;
bool array_spacing_full;
bool interleaved;
int qpitch;
struct {
int w, h, d;
} sizes[PIPE_MAX_TEXTURE_LEVELS];
};
/**
* Prepare for texture layout.
*/
static void
layout_tex_init(const struct ilo_resource *res, struct layout_tex_info *info)
{
struct ilo_screen *is = ilo_screen(res->base.screen);
const enum pipe_format bo_format = res->bo_format;
const enum intel_tiling_mode tiling = res->tiling;
const struct pipe_resource *templ = &res->base;
int last_level, lv;
memset(info, 0, sizeof(*info));
info->compressed = util_format_is_compressed(bo_format);
info->block_width = util_format_get_blockwidth(bo_format);
info->block_height = util_format_get_blockheight(bo_format);
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 113:
*
* "surface format align_i align_j
* YUV 4:2:2 formats 4 *see below
* BC1-5 4 4
* FXT1 8 4
* all other formats 4 *see below"
*
* "- align_j = 4 for any depth buffer
* - align_j = 2 for separate stencil buffer
* - align_j = 4 for any render target surface is multisampled (4x)
* - align_j = 4 for any render target surface with Surface Vertical
* Alignment = VALIGN_4
* - align_j = 2 for any render target surface with Surface Vertical
* Alignment = VALIGN_2
* - align_j = 2 for all other render target surface
* - align_j = 2 for any sampling engine surface with Surface Vertical
* Alignment = VALIGN_2
* - align_j = 4 for any sampling engine surface with Surface Vertical
* Alignment = VALIGN_4"
*
* From the Sandy Bridge PRM, volume 4 part 1, page 86:
*
* "This field (Surface Vertical Alignment) must be set to VALIGN_2 if
* the Surface Format is 96 bits per element (BPE)."
*
* They can be rephrased as
*
* align_i align_j
* compressed formats block width block height
* PIPE_FORMAT_S8_UINT 4 2
* other depth/stencil formats 4 4
* 4x multisampled 4 4
* bpp 96 4 2
* others 4 2 or 4
*/
/*
* From the Ivy Bridge PRM, volume 1 part 1, page 110:
*
* "surface defined by surface format align_i align_j
* 3DSTATE_DEPTH_BUFFER D16_UNORM 8 4
* not D16_UNORM 4 4
* 3DSTATE_STENCIL_BUFFER N/A 8 8
* SURFACE_STATE BC*, ETC*, EAC* 4 4
* FXT1 8 4
* all others (set by SURFACE_STATE)"
*
* From the Ivy Bridge PRM, volume 4 part 1, page 63:
*
* "- This field (Surface Vertical Aligment) is intended to be set to
* VALIGN_4 if the surface was rendered as a depth buffer, for a
* multisampled (4x) render target, or for a multisampled (8x)
* render target, since these surfaces support only alignment of 4.
* - Use of VALIGN_4 for other surfaces is supported, but uses more
* memory.
* - This field must be set to VALIGN_4 for all tiled Y Render Target
* surfaces.
* - Value of 1 is not supported for format YCRCB_NORMAL (0x182),
* YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190)
* - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
* must be set to VALIGN_4."
* - VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
*
* "- This field (Surface Horizontal Aligment) is intended to be set to
* HALIGN_8 only if the surface was rendered as a depth buffer with
* Z16 format or a stencil buffer, since these surfaces support only
* alignment of 8.
* - Use of HALIGN_8 for other surfaces is supported, but uses more
* memory.
* - This field must be set to HALIGN_4 if the Surface Format is BC*.
* - This field must be set to HALIGN_8 if the Surface Format is
* FXT1."
*
* They can be rephrased as
*
* align_i align_j
* compressed formats block width block height
* PIPE_FORMAT_Z16_UNORM 8 4
* PIPE_FORMAT_S8_UINT 8 8
* other depth/stencil formats 4 or 8 4
* 2x or 4x multisampled 4 or 8 4
* tiled Y 4 or 8 4 (if rt)
* PIPE_FORMAT_R32G32B32_FLOAT 4 or 8 2
* others 4 or 8 2 or 4
*/
if (info->compressed) {
/* this happens to be the case */
info->align_i = info->block_width;
info->align_j = info->block_height;
}
else if (util_format_is_depth_or_stencil(bo_format)) {
if (is->dev.gen >= ILO_GEN(7)) {
switch (bo_format) {
case PIPE_FORMAT_Z16_UNORM:
info->align_i = 8;
info->align_j = 4;
break;
case PIPE_FORMAT_S8_UINT:
info->align_i = 8;
info->align_j = 8;
break;
default:
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 319:
*
* "The 3 LSBs of both offsets (Depth Coordinate Offset Y and
* Depth Coordinate Offset X) must be zero to ensure correct
* alignment"
*
* We will make use of them and setting align_i to 8 help us meet
* the requirement.
*/
info->align_i = (templ->last_level > 0) ? 8 : 4;
info->align_j = 4;
break;
}
}
else {
switch (bo_format) {
case PIPE_FORMAT_S8_UINT:
info->align_i = 4;
info->align_j = 2;
break;
default:
info->align_i = 4;
info->align_j = 4;
break;
}
}
}
else {
const bool valign_4 = (templ->nr_samples > 1) ||
(is->dev.gen >= ILO_GEN(7) &&
(templ->bind & PIPE_BIND_RENDER_TARGET) &&
tiling == INTEL_TILING_Y);
if (valign_4)
assert(util_format_get_blocksizebits(bo_format) != 96);
info->align_i = 4;
info->align_j = (valign_4) ? 4 : 2;
}
/*
* the fact that align i and j are multiples of block width and height
* respectively is what makes the size of the bo a multiple of the block
* size, slices start at block boundaries, and many of the computations
* work.
*/
assert(info->align_i % info->block_width == 0);
assert(info->align_j % info->block_height == 0);
/* make sure align() works */
assert(util_is_power_of_two(info->align_i) &&
util_is_power_of_two(info->align_j));
assert(util_is_power_of_two(info->block_width) &&
util_is_power_of_two(info->block_height));
if (is->dev.gen >= ILO_GEN(7)) {
/*
* It is not explicitly states, but render targets are expected to be
* UMS/CMS (samples non-interleaved) and depth/stencil buffers are
* expected to be IMS (samples interleaved).
*
* See "Multisampled Surface Storage Format" field of SURFACE_STATE.
*/
if (util_format_is_depth_or_stencil(bo_format)) {
info->interleaved = true;
/*
* From the Ivy Bridge PRM, volume 1 part 1, page 111:
*
* "note that the depth buffer and stencil buffer have an implied
* value of ARYSPC_FULL"
*/
info->array_spacing_full = true;
}
else {
info->interleaved = false;
/*
* From the Ivy Bridge PRM, volume 4 part 1, page 66:
*
* "If Multisampled Surface Storage Format is MSFMT_MSS and
* Number of Multisamples is not MULTISAMPLECOUNT_1, this field
* (Surface Array Spacing) must be set to ARYSPC_LOD0."
*
* As multisampled resources are not mipmapped, we never use
* ARYSPC_FULL for them.
*/
if (templ->nr_samples > 1)
assert(templ->last_level == 0);
info->array_spacing_full = (templ->last_level > 0);
}
}
else {
/* GEN6 supports only interleaved samples */
info->interleaved = true;
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 115:
*
* "The separate stencil buffer does not support mip mapping, thus
* the storage for LODs other than LOD 0 is not needed. The
* following QPitch equation applies only to the separate stencil
* buffer:
*
* QPitch = h_0"
*
* GEN6 does not support compact spacing otherwise.
*/
info->array_spacing_full = (bo_format != PIPE_FORMAT_S8_UINT);
}
last_level = templ->last_level;
/* need at least 2 levels to compute full qpitch */
if (last_level == 0 && templ->array_size > 1 && info->array_spacing_full)
last_level++;
/* compute mip level sizes */
for (lv = 0; lv <= last_level; lv++) {
int w, h, d;
w = u_minify(templ->width0, lv);
h = u_minify(templ->height0, lv);
d = u_minify(templ->depth0, lv);
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 114:
*
* "The dimensions of the mip maps are first determined by applying
* the sizing algorithm presented in Non-Power-of-Two Mipmaps
* above. Then, if necessary, they are padded out to compression
* block boundaries."
*/
w = align(w, info->block_width);
h = align(h, info->block_height);
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 111:
*
* "If the surface is multisampled (4x), these values must be
* adjusted as follows before proceeding:
*
* W_L = ceiling(W_L / 2) * 4
* H_L = ceiling(H_L / 2) * 4"
*
* From the Ivy Bridge PRM, volume 1 part 1, page 108:
*
* "If the surface is multisampled and it is a depth or stencil
* surface or Multisampled Surface StorageFormat in SURFACE_STATE
* is MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows
* before proceeding:
*
* #samples W_L = H_L =
* 2 ceiling(W_L / 2) * 4 HL [no adjustment]
* 4 ceiling(W_L / 2) * 4 ceiling(H_L / 2) * 4
* 8 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 4
* 16 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 8"
*
* For interleaved samples (4x), where pixels
*
* (x, y ) (x+1, y )
* (x, y+1) (x+1, y+1)
*
* would be is occupied by
*
* (x, y , si0) (x+1, y , si0) (x, y , si1) (x+1, y , si1)
* (x, y+1, si0) (x+1, y+1, si0) (x, y+1, si1) (x+1, y+1, si1)
* (x, y , si2) (x+1, y , si2) (x, y , si3) (x+1, y , si3)
* (x, y+1, si2) (x+1, y+1, si2) (x, y+1, si3) (x+1, y+1, si3)
*
* Thus the need to
*
* w = align(w, 2) * 2;
* y = align(y, 2) * 2;
*/
if (info->interleaved) {
switch (templ->nr_samples) {
case 0:
case 1:
break;
case 2:
w = align(w, 2) * 2;
break;
case 4:
w = align(w, 2) * 2;
h = align(h, 2) * 2;
break;
case 8:
w = align(w, 2) * 4;
h = align(h, 2) * 2;
break;
case 16:
w = align(w, 2) * 4;
h = align(h, 2) * 4;
break;
default:
assert(!"unsupported sample count");
break;
}
}
info->sizes[lv].w = w;
info->sizes[lv].h = h;
info->sizes[lv].d = d;
}
if (templ->array_size > 1) {
const int h0 = align(info->sizes[0].h, info->align_j);
if (info->array_spacing_full) {
const int h1 = align(info->sizes[1].h, info->align_j);
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 115:
*
* "The following equation is used for surface formats other than
* compressed textures:
*
* QPitch = (h0 + h1 + 11j)"
*
* "The equation for compressed textures (BC* and FXT1 surface
* formats) follows:
*
* QPitch = (h0 + h1 + 11j) / 4"
*
* "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than
* the value calculated in the equation above, for every other
* odd Surface Height starting from 1 i.e. 1,5,9,13"
*
* From the Ivy Bridge PRM, volume 1 part 1, page 111-112:
*
* "If Surface Array Spacing is set to ARYSPC_FULL (note that the
* depth buffer and stencil buffer have an implied value of
* ARYSPC_FULL):
*
* QPitch = (h0 + h1 + 12j)
* QPitch = (h0 + h1 + 12j) / 4 (compressed)
*
* (There are many typos or missing words here...)"
*
* To access the N-th slice, an offset of (Stride * QPitch * N) is
* added to the base address. The PRM divides QPitch by 4 for
* compressed formats because the block height for those formats are
* 4, and it wants QPitch to mean the number of memory rows, as
* opposed to texel rows, between slices. Since we use texel rows in
* res->slice_offsets, we do not need to divide QPitch by 4.
*/
info->qpitch = h0 + h1 +
((is->dev.gen >= ILO_GEN(7)) ? 12 : 11) * info->align_j;
if (is->dev.gen == ILO_GEN(6) && templ->nr_samples > 1 &&
templ->height0 % 4 == 1)
info->qpitch += 4;
}
else {
info->qpitch = h0;
}
}
}
/**
* Layout a 2D texture.
*/
static void
layout_tex_2d(struct ilo_resource *res, const struct layout_tex_info *info)
{
const struct pipe_resource *templ = &res->base;
unsigned int level_x, level_y, num_slices;
int lv;
res->bo_width = 0;
res->bo_height = 0;
level_x = 0;
level_y = 0;
for (lv = 0; lv <= templ->last_level; lv++) {
const unsigned int level_w = info->sizes[lv].w;
const unsigned int level_h = info->sizes[lv].h;
int slice;
for (slice = 0; slice < templ->array_size; slice++) {
res->slice_offsets[lv][slice].x = level_x;
/* slices are qpitch apart in Y-direction */
res->slice_offsets[lv][slice].y = level_y + info->qpitch * slice;
}
/* extend the size of the monolithic bo to cover this mip level */
if (res->bo_width < level_x + level_w)
res->bo_width = level_x + level_w;
if (res->bo_height < level_y + level_h)
res->bo_height = level_y + level_h;
/* MIPLAYOUT_BELOW */
if (lv == 1)
level_x += align(level_w, info->align_i);
else
level_y += align(level_h, info->align_j);
}
num_slices = templ->array_size;
/* samples of the same index are stored in a slice */
if (templ->nr_samples > 1 && !info->interleaved)
num_slices *= templ->nr_samples;
/* we did not take slices into consideration in the computation above */
res->bo_height += info->qpitch * (num_slices - 1);
}
/**
* Layout a 3D texture.
*/
static void
layout_tex_3d(struct ilo_resource *res, const struct layout_tex_info *info)
{
const struct pipe_resource *templ = &res->base;
unsigned int level_y;
int lv;
res->bo_width = 0;
res->bo_height = 0;
level_y = 0;
for (lv = 0; lv <= templ->last_level; lv++) {
const unsigned int level_w = info->sizes[lv].w;
const unsigned int level_h = info->sizes[lv].h;
const unsigned int level_d = info->sizes[lv].d;
const unsigned int slice_pitch = align(level_w, info->align_i);
const unsigned int slice_qpitch = align(level_h, info->align_j);
const unsigned int num_slices_per_row = 1 << lv;
int slice;
for (slice = 0; slice < level_d; slice += num_slices_per_row) {
int i;
for (i = 0; i < num_slices_per_row && slice + i < level_d; i++) {
res->slice_offsets[lv][slice + i].x = slice_pitch * i;
res->slice_offsets[lv][slice + i].y = level_y;
}
/* move on to the next slice row */
level_y += slice_qpitch;
}
/* rightmost slice */
slice = MIN2(num_slices_per_row, level_d) - 1;
/* extend the size of the monolithic bo to cover this slice */
if (res->bo_width < slice_pitch * slice + level_w)
res->bo_width = slice_pitch * slice + level_w;
if (lv == templ->last_level)
res->bo_height = (level_y - slice_qpitch) + level_h;
}
}
/**
* Guess the texture size. For large textures, the errors are relative small.
*/
static size_t
guess_tex_size(const struct pipe_resource *templ,
enum intel_tiling_mode tiling)
{
int bo_width, bo_height, bo_stride;
/* HALIGN_8 and VALIGN_4 */
bo_width = align(templ->width0, 8);
bo_height = align(templ->height0, 4);
if (templ->target == PIPE_TEXTURE_3D) {
const int num_rows = util_next_power_of_two(templ->depth0);
int lv, sum;
sum = bo_height * templ->depth0;
for (lv = 1; lv <= templ->last_level; lv++)
sum += u_minify(bo_height, lv) * u_minify(num_rows, lv);
bo_height = sum;
}
else if (templ->last_level > 0) {
/* MIPLAYOUT_BELOW, ignore qpich */
bo_height = (bo_height + u_minify(bo_height, 1)) * templ->array_size;
}
bo_stride = util_format_get_stride(templ->format, bo_width);
switch (tiling) {
case INTEL_TILING_X:
bo_stride = align(bo_stride, 512);
bo_height = align(bo_height, 8);
break;
case INTEL_TILING_Y:
bo_stride = align(bo_stride, 128);
bo_height = align(bo_height, 32);
break;
default:
bo_height = align(bo_height, 2);
break;
}
return util_format_get_2d_size(templ->format, bo_stride, bo_height);
}
static enum intel_tiling_mode
get_tex_tiling(const struct ilo_resource *res)
{
const struct pipe_resource *templ = &res->base;
const enum pipe_format bo_format = res->bo_format;
/*
* From the Sandy Bridge PRM, volume 1 part 2, page 32:
*
* "Display/Overlay Y-Major not supported.
* X-Major required for Async Flips"
*/
if (unlikely(templ->bind & PIPE_BIND_SCANOUT))
return INTEL_TILING_X;
/*
* From the Sandy Bridge PRM, volume 3 part 2, page 158:
*
* "The cursor surface address must be 4K byte aligned. The cursor must
* be in linear memory, it cannot be tiled."
*/
if (unlikely(templ->bind & PIPE_BIND_CURSOR))
return INTEL_TILING_NONE;
/*
* From the Ivy Bridge PRM, volume 4 part 1, page 76:
*
* "The MCS surface must be stored as Tile Y."
*/
if (templ->bind & ILO_BIND_MCS)
return INTEL_TILING_Y;
/*
* From the Sandy Bridge PRM, volume 2 part 1, page 318:
*
* "[DevSNB+]: This field (Tiled Surface) must be set to TRUE. Linear
* Depth Buffer is not supported."
*
* "The Depth Buffer, if tiled, must use Y-Major tiling."
*/
if (templ->bind & PIPE_BIND_DEPTH_STENCIL) {
/* separate stencil uses W-tiling but we do not know how to specify that */
return (bo_format == PIPE_FORMAT_S8_UINT) ?
INTEL_TILING_NONE : INTEL_TILING_Y;
}
if (templ->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) {
enum intel_tiling_mode tiling = INTEL_TILING_NONE;
/*
* From the Sandy Bridge PRM, volume 1 part 2, page 32:
*
* "NOTE: 128BPE Format Color buffer ( render target ) MUST be
* either TileX or Linear."
*
* Also, heuristically set a minimum width/height for enabling tiling.
*/
if (util_format_get_blocksizebits(bo_format) == 128 &&
(templ->bind & PIPE_BIND_RENDER_TARGET) && templ->width0 >= 64)
tiling = INTEL_TILING_X;
else if ((templ->width0 >= 32 && templ->height0 >= 16) ||
(templ->width0 >= 16 && templ->height0 >= 32))
tiling = INTEL_TILING_Y;
/* make sure the bo can be mapped through GTT if tiled */
if (tiling != INTEL_TILING_NONE) {
/*
* Usually only the first 256MB of the GTT is mappable.
*
* See also how intel_context::max_gtt_map_object_size is calculated.
*/
const size_t mappable_gtt_size = 256 * 1024 * 1024;
const size_t size = guess_tex_size(templ, tiling);
/* be conservative */
if (size > mappable_gtt_size / 4)
tiling = INTEL_TILING_NONE;
}
return tiling;
}
return INTEL_TILING_NONE;
}
static void
init_texture(struct ilo_resource *res)
{
struct layout_tex_info info;
res->bo_format = res->base.format;
/* determine tiling first as it may affect the layout */
res->tiling = get_tex_tiling(res);
layout_tex_init(res, &info);
res->compressed = info.compressed;
res->block_width = info.block_width;
res->block_height = info.block_height;
res->halign_8 = (info.align_i == 8);
res->valign_4 = (info.align_j == 4);
res->array_spacing_full = info.array_spacing_full;
res->interleaved = info.interleaved;
switch (res->base.target) {
case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_CUBE:
case PIPE_TEXTURE_RECT:
case PIPE_TEXTURE_1D_ARRAY:
case PIPE_TEXTURE_2D_ARRAY:
case PIPE_TEXTURE_CUBE_ARRAY:
layout_tex_2d(res, &info);
break;
case PIPE_TEXTURE_3D:
layout_tex_3d(res, &info);
break;
default:
assert(!"unknown resource target");
break;
}
/*
* From the Sandy Bridge PRM, volume 1 part 2, page 22:
*
* "A 4KB tile is subdivided into 8-high by 8-wide array of Blocks for
* W-Major Tiles (W Tiles). Each Block is 8 rows by 8 bytes."
*
* Since we ask for INTEL_TILING_NONE instead lf INTEL_TILING_W, we need to
* manually align the bo width and height to the tile boundaries.
*/
if (res->bo_format == PIPE_FORMAT_S8_UINT) {
res->bo_width = align(res->bo_width, 64);
res->bo_height = align(res->bo_height, 64);
}
/* in blocks */
assert(res->bo_width % info.block_width == 0);
assert(res->bo_height % info.block_height == 0);
res->bo_width /= info.block_width;
res->bo_height /= info.block_height;
res->bo_cpp = util_format_get_blocksize(res->bo_format);
}
static void
init_buffer(struct ilo_resource *res)
{
res->bo_format = res->base.format;
res->bo_width = res->base.width0;
res->bo_height = 1;
res->bo_cpp = 1;
res->bo_stride = 0;
res->tiling = INTEL_TILING_NONE;
res->compressed = false;
res->block_width = 1;
res->block_height = 1;
res->halign_8 = false;
res->valign_4 = false;
res->array_spacing_full = false;
res->interleaved = false;
}
static struct pipe_resource *
create_resource(struct pipe_screen *screen,
const struct pipe_resource *templ,
struct winsys_handle *handle)
{
struct ilo_resource *res;
res = CALLOC_STRUCT(ilo_resource);
if (!res)
return NULL;
res->base = *templ;
res->base.screen = screen;
pipe_reference_init(&res->base.reference, 1);
res->handle = handle;
if (!alloc_slice_offsets(res)) {
FREE(res);
return NULL;
}
if (templ->target == PIPE_BUFFER)
init_buffer(res);
else
init_texture(res);
if (!realloc_bo(res)) {
free_slice_offsets(res);
FREE(res);
return NULL;
}
return &res->base;
}
static boolean
ilo_can_create_resource(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
/*
* We do not know if we will fail until we try to allocate the bo.
* So just set a limit on the texture size.
*/
const size_t max_size = 1 * 1024 * 1024 * 1024;
const size_t size = guess_tex_size(templ, INTEL_TILING_Y);
return (size <= max_size);
}
static struct pipe_resource *
ilo_resource_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
return create_resource(screen, templ, NULL);
}
static struct pipe_resource *
ilo_resource_from_handle(struct pipe_screen *screen,
const struct pipe_resource *templ,
struct winsys_handle *handle)
{
return create_resource(screen, templ, handle);
}
static boolean
ilo_resource_get_handle(struct pipe_screen *screen,
struct pipe_resource *r,
struct winsys_handle *handle)
{
struct ilo_resource *res = ilo_resource(r);
int err;
err = res->bo->export_handle(res->bo, handle);
return !err;
}
static void
ilo_resource_destroy(struct pipe_screen *screen,
struct pipe_resource *r)
{
struct ilo_resource *res = ilo_resource(r);
free_slice_offsets(res);
res->bo->unreference(res->bo);
FREE(res);
}
/**
* Initialize resource-related functions.
*/
void
ilo_init_resource_functions(struct ilo_screen *is)
{
is->base.can_create_resource = ilo_can_create_resource;
is->base.resource_create = ilo_resource_create;
is->base.resource_from_handle = ilo_resource_from_handle;
is->base.resource_get_handle = ilo_resource_get_handle;
is->base.resource_destroy = ilo_resource_destroy;
}
/**
* Initialize transfer-related functions.
*/
void
ilo_init_transfer_functions(struct ilo_context *ilo)
{
ilo->base.transfer_map = ilo_transfer_map;
ilo->base.transfer_flush_region = ilo_transfer_flush_region;
ilo->base.transfer_unmap = ilo_transfer_unmap;
ilo->base.transfer_inline_write = ilo_transfer_inline_write;
}
/**
* Return the offset (in bytes) to a slice within the bo.
*
* When tile_aligned is true, the offset is to the tile containing the start
* address of the slice. x_offset and y_offset are offsets (in pixels) from
* the tile start to slice start. x_offset is always a multiple of 4 and
* y_offset is always a multiple of 2.
*/
unsigned
ilo_resource_get_slice_offset(const struct ilo_resource *res,
int level, int slice, bool tile_aligned,
unsigned *x_offset, unsigned *y_offset)
{
const unsigned x = res->slice_offsets[level][slice].x / res->block_width;
const unsigned y = res->slice_offsets[level][slice].y / res->block_height;
unsigned tile_w, tile_h, tile_size, row_size;
unsigned slice_offset;
/* see the Sandy Bridge PRM, volume 1 part 2, page 24 */
switch (res->tiling) {
case INTEL_TILING_NONE:
tile_w = res->bo_cpp;
tile_h = 1;
break;
case INTEL_TILING_X:
tile_w = 512;
tile_h = 8;
break;
case INTEL_TILING_Y:
tile_w = 128;
tile_h = 32;
break;
default:
assert(!"unknown tiling");
tile_w = res->bo_cpp;
tile_h = 1;
break;
}
tile_size = tile_w * tile_h;
row_size = res->bo_stride * tile_h;
/*
* for non-tiled resources, this is equivalent to
*
* slice_offset = y * res->bo_stride + x * res->bo_cpp;
*/
slice_offset =
row_size * (y / tile_h) + tile_size * (x * res->bo_cpp / tile_w);
/*
* Since res->bo_stride is a multiple of tile_w, slice_offset should be
* aligned at this point.
*/
assert(slice_offset % tile_size == 0);
if (tile_aligned) {
/*
* because of the possible values of align_i and align_j in
* layout_tex_init(), x_offset must be a multiple of 4 and y_offset must
* be a multiple of 2.
*/
if (x_offset) {
assert(tile_w % res->bo_cpp == 0);
*x_offset = (x % (tile_w / res->bo_cpp)) * res->block_width;
assert(*x_offset % 4 == 0);
}
if (y_offset) {
*y_offset = (y % tile_h) * res->block_height;
assert(*y_offset % 2 == 0);
}
}
else {
const unsigned tx = (x * res->bo_cpp) % tile_w;
const unsigned ty = y % tile_h;
switch (res->tiling) {
case INTEL_TILING_NONE:
assert(tx == 0 && ty == 0);
break;
case INTEL_TILING_X:
slice_offset += tile_w * ty + tx;
break;
case INTEL_TILING_Y:
slice_offset += tile_h * 16 * (tx / 16) + ty * 16 + (tx % 16);
break;
}
if (x_offset)
*x_offset = 0;
if (y_offset)
*y_offset = 0;
}
return slice_offset;
}
|