1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
|
/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
/*
* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Rob Clark <robclark@freedesktop.org>
*/
#ifndef FREEDRENO_CONTEXT_H_
#define FREEDRENO_CONTEXT_H_
#include "pipe/p_context.h"
#include "indices/u_primconvert.h"
#include "util/u_blitter.h"
#include "util/list.h"
#include "util/u_slab.h"
#include "util/u_string.h"
#include "freedreno_batch.h"
#include "freedreno_screen.h"
#include "freedreno_gmem.h"
#include "freedreno_util.h"
#define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
struct fd_vertex_stateobj;
struct fd_texture_stateobj {
struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
unsigned num_textures;
unsigned valid_textures;
struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
unsigned num_samplers;
unsigned valid_samplers;
};
struct fd_program_stateobj {
void *vp, *fp;
/* rest only used by fd2.. split out: */
uint8_t num_exports;
/* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
* for TGSI_SEMANTIC_GENERIC. Special vs exports (position and point-
* size) are not included in this
*/
uint8_t export_linkage[63];
};
struct fd_constbuf_stateobj {
struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
uint32_t enabled_mask;
uint32_t dirty_mask;
};
struct fd_vertexbuf_stateobj {
struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
unsigned count;
uint32_t enabled_mask;
uint32_t dirty_mask;
};
struct fd_vertex_stateobj {
struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
unsigned num_elements;
};
struct fd_streamout_stateobj {
struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
unsigned num_targets;
/* Track offset from vtxcnt for streamout data. This counter
* is just incremented by # of vertices on each draw until
* reset or new streamout buffer bound.
*
* When we eventually have GS, the CPU won't actually know the
* number of vertices per draw, so I think we'll have to do
* something more clever.
*/
unsigned offsets[PIPE_MAX_SO_BUFFERS];
};
/* group together the vertex and vertexbuf state.. for ease of passing
* around, and because various internal operations (gmem<->mem, etc)
* need their own vertex state:
*/
struct fd_vertex_state {
struct fd_vertex_stateobj *vtx;
struct fd_vertexbuf_stateobj vertexbuf;
};
/* Bitmask of stages in rendering that a particular query query is
* active. Queries will be automatically started/stopped (generating
* additional fd_hw_sample_period's) on entrance/exit from stages that
* are applicable to the query.
*
* NOTE: set the stage to NULL at end of IB to ensure no query is still
* active. Things aren't going to work out the way you want if a query
* is active across IB's (or between tile IB and draw IB)
*/
enum fd_render_stage {
FD_STAGE_NULL = 0x01,
FD_STAGE_DRAW = 0x02,
FD_STAGE_CLEAR = 0x04,
/* TODO before queries which include MEM2GMEM or GMEM2MEM will
* work we will need to call fd_hw_query_prepare() from somewhere
* appropriate so that queries in the tiling IB get backed with
* memory to write results to.
*/
FD_STAGE_MEM2GMEM = 0x08,
FD_STAGE_GMEM2MEM = 0x10,
/* used for driver internal draws (ie. util_blitter_blit()): */
FD_STAGE_BLIT = 0x20,
FD_STAGE_ALL = 0xff,
};
#define MAX_HW_SAMPLE_PROVIDERS 4
struct fd_hw_sample_provider;
struct fd_hw_sample;
struct fd_context {
struct pipe_context base;
struct fd_device *dev;
struct fd_screen *screen;
struct blitter_context *blitter;
struct primconvert_context *primconvert;
/* slab for pipe_transfer allocations: */
struct util_slab_mempool transfer_pool;
/* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
struct util_slab_mempool sample_pool;
struct util_slab_mempool sample_period_pool;
/* next sample offset.. incremented for each sample in the batch/
* submit, reset to zero on next submit.
*/
uint32_t next_sample_offset;
/* sample-providers for hw queries: */
const struct fd_hw_sample_provider *sample_providers[MAX_HW_SAMPLE_PROVIDERS];
/* cached samples (in case multiple queries need to reference
* the same sample snapshot)
*/
struct fd_hw_sample *sample_cache[MAX_HW_SAMPLE_PROVIDERS];
/* which sample providers were active in the current batch: */
uint32_t active_providers;
/* tracking for current stage, to know when to start/stop
* any active queries:
*/
enum fd_render_stage stage;
/* list of active queries: */
struct list_head active_queries;
/* list of queries that are not active, but were active in the
* current submit:
*/
struct list_head current_queries;
/* current query result bo and tile stride: */
struct fd_bo *query_bo;
uint32_t query_tile_stride;
/* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
* DI_PT_x value to use for draw initiator. There are some
* slight differences between generation:
*/
const uint8_t *primtypes;
uint32_t primtype_mask;
/* shaders used by clear, and gmem->mem blits: */
struct fd_program_stateobj solid_prog; // TODO move to screen?
/* shaders used by mem->gmem blits: */
struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
struct fd_program_stateobj blit_z, blit_zs;
/* Stats/counters:
*/
struct {
uint64_t prims_emitted;
uint64_t prims_generated;
uint64_t draw_calls;
uint64_t batch_total, batch_sysmem, batch_gmem, batch_restore;
} stats;
/* Current batch.. the rule here is that you can deref ctx->batch
* in codepaths from pipe_context entrypoints. But not in code-
* paths from fd_batch_flush() (basically, the stuff that gets
* called from GMEM code), since in those code-paths the batch
* you care about is not necessarily the same as ctx->batch.
*/
struct fd_batch *batch;
/* Keep track if WAIT_FOR_IDLE is needed for registers we need
* to update via RMW:
*/
bool needs_wfi;
/* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION? At least on a3xx
* it is not a banked context register, so it needs a WFI to update.
* Keep track if it has actually changed, to avoid unneeded WFI.
* */
bool needs_rb_fbd;
struct pipe_scissor_state scissor;
/* we don't have a disable/enable bit for scissor, so instead we keep
* a disabled-scissor state which matches the entire bound framebuffer
* and use that when scissor is not enabled.
*/
struct pipe_scissor_state disabled_scissor;
/* Current gmem/tiling configuration.. gets updated on render_tiles()
* if out of date with current maximal-scissor/cpp:
*
* (NOTE: this is kind of related to the batch, but moving it there
* means we'd always have to recalc tiles ever batch)
*/
struct fd_gmem_stateobj gmem;
struct fd_vsc_pipe pipe[8];
struct fd_tile tile[512];
/* which state objects need to be re-emit'd: */
enum {
FD_DIRTY_BLEND = (1 << 0),
FD_DIRTY_RASTERIZER = (1 << 1),
FD_DIRTY_ZSA = (1 << 2),
FD_DIRTY_FRAGTEX = (1 << 3),
FD_DIRTY_VERTTEX = (1 << 4),
FD_DIRTY_TEXSTATE = (1 << 5),
FD_SHADER_DIRTY_VP = (1 << 6),
FD_SHADER_DIRTY_FP = (1 << 7),
/* skip geom/tcs/tes/compute */
FD_DIRTY_PROG = FD_SHADER_DIRTY_FP | FD_SHADER_DIRTY_VP,
FD_DIRTY_BLEND_COLOR = (1 << 12),
FD_DIRTY_STENCIL_REF = (1 << 13),
FD_DIRTY_SAMPLE_MASK = (1 << 14),
FD_DIRTY_FRAMEBUFFER = (1 << 15),
FD_DIRTY_STIPPLE = (1 << 16),
FD_DIRTY_VIEWPORT = (1 << 17),
FD_DIRTY_CONSTBUF = (1 << 18),
FD_DIRTY_VTXSTATE = (1 << 19),
FD_DIRTY_VTXBUF = (1 << 20),
FD_DIRTY_INDEXBUF = (1 << 21),
FD_DIRTY_SCISSOR = (1 << 22),
FD_DIRTY_STREAMOUT = (1 << 23),
FD_DIRTY_UCP = (1 << 24),
FD_DIRTY_BLEND_DUAL = (1 << 25),
} dirty;
struct pipe_blend_state *blend;
struct pipe_rasterizer_state *rasterizer;
struct pipe_depth_stencil_alpha_state *zsa;
struct fd_texture_stateobj verttex, fragtex;
struct fd_program_stateobj prog;
struct fd_vertex_state vtx;
struct pipe_blend_color blend_color;
struct pipe_stencil_ref stencil_ref;
unsigned sample_mask;
struct pipe_poly_stipple stipple;
struct pipe_viewport_state viewport;
struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
struct pipe_index_buffer indexbuf;
struct fd_streamout_stateobj streamout;
struct pipe_clip_state ucp;
struct pipe_query *cond_query;
bool cond_cond; /* inverted rendering condition */
uint cond_mode;
/* Are we in process of shadowing a resource? Used to detect recursion
* in transfer_map, and skip unneeded synchronization.
*/
bool in_shadow;
/* Ie. in blit situation where we no longer care about previous framebuffer
* contents. Main point is to eliminate blits from fd_try_shadow_resource().
* For example, in case of texture upload + gen-mipmaps.
*/
bool discard;
struct pipe_debug_callback debug;
/* GMEM/tile handling fxns: */
void (*emit_tile_init)(struct fd_batch *batch);
void (*emit_tile_prep)(struct fd_batch *batch, struct fd_tile *tile);
void (*emit_tile_mem2gmem)(struct fd_batch *batch, struct fd_tile *tile);
void (*emit_tile_renderprep)(struct fd_batch *batch, struct fd_tile *tile);
void (*emit_tile_gmem2mem)(struct fd_batch *batch, struct fd_tile *tile);
/* optional, for GMEM bypass: */
void (*emit_sysmem_prep)(struct fd_batch *batch);
/* draw: */
bool (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info);
void (*clear)(struct fd_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil);
/* constant emit: (note currently not used/needed for a2xx) */
void (*emit_const)(struct fd_ringbuffer *ring, enum shader_t type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc);
/* emit bo addresses as constant: */
void (*emit_const_bo)(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets);
/* indirect-branch emit: */
void (*emit_ib)(struct fd_ringbuffer *ring, struct fd_ringbuffer *target);
};
static inline struct fd_context *
fd_context(struct pipe_context *pctx)
{
return (struct fd_context *)pctx;
}
static inline struct pipe_scissor_state *
fd_context_get_scissor(struct fd_context *ctx)
{
if (ctx->rasterizer && ctx->rasterizer->scissor)
return &ctx->scissor;
return &ctx->disabled_scissor;
}
static inline bool
fd_supported_prim(struct fd_context *ctx, unsigned prim)
{
return (1 << prim) & ctx->primtype_mask;
}
static inline void
fd_reset_wfi(struct fd_context *ctx)
{
ctx->needs_wfi = true;
}
/* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
* been one since last draw:
*/
static inline void
fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring)
{
if (ctx->needs_wfi) {
OUT_WFI(ring);
ctx->needs_wfi = false;
}
}
/* emit a CP_EVENT_WRITE:
*/
static inline void
fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring,
enum vgt_event_type evt)
{
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, evt);
fd_reset_wfi(ctx);
}
struct pipe_context * fd_context_init(struct fd_context *ctx,
struct pipe_screen *pscreen, const uint8_t *primtypes,
void *priv);
void fd_context_destroy(struct pipe_context *pctx);
#endif /* FREEDRENO_CONTEXT_H_ */
|