summaryrefslogtreecommitdiffstats
path: root/src/gallium/auxiliary/tgsi/tgsi_ppc.c
blob: 9d7de41fe7f80f0b6d903c4b1b4a08e1732cea5b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
/**************************************************************************
 * 
 * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 * 
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 * 
 **************************************************************************/

/**
 * TGSI to PowerPC code generation.
 */

#include "pipe/p_config.h"

#if defined(PIPE_ARCH_PPC)

#include "pipe/p_debug.h"
#include "pipe/p_shader_tokens.h"
#include "util/u_math.h"
#include "util/u_sse.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_util.h"
#include "tgsi_exec.h"
#include "tgsi_ppc.h"
#include "rtasm/rtasm_ppc.h"



#define FOR_EACH_CHANNEL( CHAN )\
   for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)

#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
   ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))

#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
   if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))

#define FOR_EACH_DST0_ENABLED_CHANNEL( INST, CHAN )\
   FOR_EACH_CHANNEL( CHAN )\
      IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )

#define CHAN_X 0
#define CHAN_Y 1
#define CHAN_Z 2
#define CHAN_W 3

#define TEMP_ONE_I   TGSI_EXEC_TEMP_ONE_I
#define TEMP_ONE_C   TGSI_EXEC_TEMP_ONE_C

#define TEMP_R0   TGSI_EXEC_TEMP_R0
#define TEMP_ADDR TGSI_EXEC_TEMP_ADDR


/**
 * Context/state used during code gen.
 */
struct gen_context
{
   struct ppc_function *f;
   int inputs_reg;    /**< GP register pointing to input params */
   int outputs_reg;   /**< GP register pointing to output params */
   int temps_reg;     /**< GP register pointing to temporary "registers" */
   int immed_reg;     /**< GP register pointing to immediates buffer */
   int const_reg;     /**< GP register pointing to constants buffer */

   int one_vec;       /**< vector register with {1.0, 1.0, 1.0, 1.0} */
   int bit31_vec;     /**< vector register with {1<<31, 1<<31, 1<<31, 1<<31} */
};


/**
 * Return index of vector register containing {1.0, 1.0, 1.0, 1.0}.
 */
static int
gen_one_vec(struct gen_context *gen)
{
   if (gen->one_vec < 0) {
      gen->one_vec = ppc_allocate_vec_register(gen->f);
      ppc_vload_float(gen->f, gen->one_vec, 1.0f);
   }
   return gen->one_vec;
}

/**
 * Return index of vector register containing {1<<31, 1<<31, 1<<31, 1<<31}.
 */
static int
gen_get_bit31_vec(struct gen_context *gen)
{
   if (gen->bit31_vec < 0) {
      gen->bit31_vec = ppc_allocate_vec_register(gen->f);
      ppc_vspltisw(gen->f, gen->bit31_vec, -1);
      ppc_vslw(gen->f, gen->bit31_vec, gen->bit31_vec, gen->bit31_vec);
   }
   return gen->bit31_vec;
}



/**
 * Register fetch, put result in 'dst_vec'.
 */
static void
emit_fetch(struct gen_context *gen,
           unsigned dst_vec,
           const struct tgsi_full_src_register *reg,
           const unsigned chan_index)
{
   uint swizzle = tgsi_util_get_full_src_register_extswizzle(reg, chan_index);

   switch (swizzle) {
   case TGSI_EXTSWIZZLE_X:
   case TGSI_EXTSWIZZLE_Y:
   case TGSI_EXTSWIZZLE_Z:
   case TGSI_EXTSWIZZLE_W:
      switch (reg->SrcRegister.File) {
      case TGSI_FILE_INPUT:
         {
            int offset_reg = ppc_allocate_register(gen->f);
            int offset = (reg->SrcRegister.Index * 4 + swizzle) * 16;
            ppc_li(gen->f, offset_reg, offset);
            ppc_lvx(gen->f, dst_vec, gen->inputs_reg, offset_reg);
            ppc_release_register(gen->f, offset_reg);
         }
         break;
      case TGSI_FILE_TEMPORARY:
         {
            int offset_reg = ppc_allocate_register(gen->f);
            int offset = (reg->SrcRegister.Index * 4 + swizzle) * 16;
            ppc_li(gen->f, offset_reg, offset);
            ppc_lvx(gen->f, dst_vec, gen->temps_reg, offset_reg);
            ppc_release_register(gen->f, offset_reg);
         }
         break;
      case TGSI_FILE_IMMEDIATE:
         {
            int offset_reg = ppc_allocate_register(gen->f);
            int offset = (reg->SrcRegister.Index * 4 + swizzle) * 16;
            ppc_li(gen->f, offset_reg, offset);
            ppc_lvx(gen->f, dst_vec, gen->immed_reg, offset_reg);
            ppc_release_register(gen->f, offset_reg);
         }
         break;
      case TGSI_FILE_CONSTANT:
         {
            int offset_reg = ppc_allocate_register(gen->f);
            int offset = (reg->SrcRegister.Index * 4 + swizzle) * 4;
            ppc_li(gen->f, offset_reg, offset);
            /* Load 4-byte word into vector register.
             * The vector slot depends on the effective address we load from.
             * We know that our constants start at a 16-byte boundary so we
             * know that 'swizzle' tells us which vector slot will have the
             * loaded word.  The other vector slots will be undefined.
             */
            ppc_lvewx(gen->f, dst_vec, gen->const_reg, offset_reg);
            /* splat word[swizzle] across the vector reg */
            ppc_vspltw(gen->f, dst_vec, dst_vec, swizzle);
            ppc_release_register(gen->f, offset_reg);
         }
         break;
      default:
         assert( 0 );
      }
      break;
   case TGSI_EXTSWIZZLE_ZERO:
      ppc_vload_float(gen->f, dst_vec, 0.0f);
      break;
   case TGSI_EXTSWIZZLE_ONE:
      {
         int one_vec = gen_one_vec(gen);
         ppc_vecmove(gen->f, dst_vec, one_vec);
      }
      break;
   default:
      assert( 0 );
   }

   {
      uint sign_op = tgsi_util_get_full_src_register_sign_mode(reg, chan_index);
      if (sign_op != TGSI_UTIL_SIGN_KEEP) {
         int bit31_vec = gen_get_bit31_vec(gen);

         switch (sign_op) {
         case TGSI_UTIL_SIGN_CLEAR:
            /* vec = vec & ~bit31 */
            ppc_vandc(gen->f, dst_vec, dst_vec, bit31_vec);
            break;
         case TGSI_UTIL_SIGN_SET:
            /* vec = vec | bit31 */
            ppc_vor(gen->f, dst_vec, dst_vec, bit31_vec);
            break;
         case TGSI_UTIL_SIGN_TOGGLE:
            /* vec = vec ^ bit31 */
            ppc_vxor(gen->f, dst_vec, dst_vec, bit31_vec);
            break;
         default:
            assert(0);
         }
      }
   }
}

#define FETCH( GEN, INST, DST_VEC, SRC_REG, CHAN ) \
   emit_fetch( GEN, DST_VEC, &(INST).FullSrcRegisters[SRC_REG], CHAN )



/**
 * Register store.  Store 'src_vec' at location indicated by 'reg'.
 */
static void
emit_store(struct gen_context *gen,
           unsigned src_vec,
           const struct tgsi_full_dst_register *reg,
           const struct tgsi_full_instruction *inst,
           unsigned chan_index)
{
   switch (reg->DstRegister.File) {
   case TGSI_FILE_OUTPUT:
      {
         int offset_reg = ppc_allocate_register(gen->f);
         int offset = (reg->DstRegister.Index * 4 + chan_index) * 16;
         ppc_li(gen->f, offset_reg, offset);
         ppc_stvx(gen->f, src_vec, gen->outputs_reg, offset_reg);
         ppc_release_register(gen->f, offset_reg);
      }
      break;
   case TGSI_FILE_TEMPORARY:
      {
         int offset_reg = ppc_allocate_register(gen->f);
         int offset = (reg->DstRegister.Index * 4 + chan_index) * 16;
         ppc_li(gen->f, offset_reg, offset);
         ppc_stvx(gen->f, src_vec, gen->temps_reg, offset_reg);
         ppc_release_register(gen->f, offset_reg);
      }
      break;
#if 0
   case TGSI_FILE_ADDRESS:
      emit_addrs(
         func,
         xmm,
         reg->DstRegister.Index,
         chan_index );
      break;
#endif
   default:
      assert( 0 );
   }

#if 0
   switch( inst->Instruction.Saturate ) {
   case TGSI_SAT_NONE:
      break;

   case TGSI_SAT_ZERO_ONE:
      /* assert( 0 ); */
      break;

   case TGSI_SAT_MINUS_PLUS_ONE:
      assert( 0 );
      break;
   }
#endif
}


#define STORE( GEN, INST, XMM, INDEX, CHAN )\
   emit_store( GEN, XMM, &(INST).FullDstRegisters[INDEX], &(INST), CHAN )



static void
emit_scalar_unaryop(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int v0 = ppc_allocate_vec_register(gen->f);
   int v1 = ppc_allocate_vec_register(gen->f);
   uint chan_index;

   FETCH(gen, *inst, v0, 0, CHAN_X);

   switch (inst->Instruction.Opcode) {
   case TGSI_OPCODE_RSQ:
      /* v1 = 1.0 / sqrt(v0) */
      ppc_vrsqrtefp(gen->f, v1, v0);
      break;
   case TGSI_OPCODE_RCP:
      /* v1 = 1.0 / v0 */
      ppc_vrefp(gen->f, v1, v0);
      break;
   default:
      assert(0);
   }

   FOR_EACH_DST0_ENABLED_CHANNEL( *inst, chan_index ) {
      STORE(gen, *inst, v1, 0, chan_index);
   }
   ppc_release_vec_register(gen->f, v0);
   ppc_release_vec_register(gen->f, v1);
}


static void
emit_unaryop(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int v0 = ppc_allocate_vec_register(gen->f);
   uint chan_index;
   FOR_EACH_DST0_ENABLED_CHANNEL(*inst, chan_index) {
      FETCH(gen, *inst, 0, 0, chan_index);   /* v0 = srcreg[0] */
      switch (inst->Instruction.Opcode) {
      case TGSI_OPCODE_ABS:
         /* turn off the most significant bit of each vector float word */
         {
            int v1 = ppc_allocate_vec_register(gen->f);
            ppc_vspltisw(gen->f, v1, -1);  /* v1 = {-1, -1, -1, -1} */
            ppc_vslw(gen->f, v1, v1, v1);  /* v1 = {1<<31, 1<<31, 1<<31, 1<<31} */
            ppc_vandc(gen->f, v0, v0, v1); /* v0 = v0 & ~v1 */
            ppc_release_vec_register(gen->f, v1);
         }
         break;
      case TGSI_OPCODE_FLOOR:
         ppc_vrfim(gen->f, v0, v0);         /* v0 = floor(v0) */
         break;
      case TGSI_OPCODE_FRAC:
         {
            int v1 = ppc_allocate_vec_register(gen->f);
            ppc_vrfim(gen->f, v1, v0);         /* v1 = floor(v0) */
            ppc_vsubfp(gen->f, v0, v0, v1);    /* v0 = v0 - v1 */
            ppc_release_vec_register(gen->f, v1);
         }
         break;
      case TGSI_OPCODE_EXPBASE2:
         ppc_vexptefp(gen->f, v0, v0);      /* v0 = 2^v0 */
         break;
      case TGSI_OPCODE_LOGBASE2:
         /* XXX this may be broken! */
         ppc_vlogefp(gen->f, v0, v0);      /* v0 = log2(v0) */
         break;
      case TGSI_OPCODE_MOV:
         /* nothing */
         break;
      default:
         assert(0);
      }
      STORE(gen, *inst, v0, 0, chan_index);   /* store v0 */
   }
   ppc_release_vec_register(gen->f, v0);
}


static void
emit_binop(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int v0 = ppc_allocate_vec_register(gen->f);
   int v1 = ppc_allocate_vec_register(gen->f);
   int v2 = ppc_allocate_vec_register(gen->f);
   uint chan_index;
   FOR_EACH_DST0_ENABLED_CHANNEL(*inst, chan_index) {
      FETCH(gen, *inst, v0, 0, chan_index);   /* v0 = srcreg[0] */
      FETCH(gen, *inst, v1, 1, chan_index);   /* v1 = srcreg[1] */
      switch (inst->Instruction.Opcode) {
      case TGSI_OPCODE_ADD:
         ppc_vaddfp(gen->f, v2, v0, v1);
         break;
      case TGSI_OPCODE_SUB:
         ppc_vsubfp(gen->f, v2, v0, v1);
         break;
      case TGSI_OPCODE_MUL:
         ppc_vxor(gen->f, v2, v2, v2);        /* v2 = {0, 0, 0, 0} */
         ppc_vmaddfp(gen->f, v2, v0, v1, v2); /* v2 = v0 * v1 + v0 */
         break;
      case TGSI_OPCODE_MIN:
         ppc_vminfp(gen->f, v2, v0, v1);
         break;
      case TGSI_OPCODE_MAX:
         ppc_vmaxfp(gen->f, v2, v0, v1);
         break;
      default:
         assert(0);
      }
      STORE(gen, *inst, v2, 0, chan_index);   /* store v2 */
   }
   ppc_release_vec_register(gen->f, v0);
   ppc_release_vec_register(gen->f, v1);
   ppc_release_vec_register(gen->f, v2);
}


/**
 * Vector comparisons, resulting in 1.0 or 0.0 values.
 */
static void
emit_inequality(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int v0 = ppc_allocate_vec_register(gen->f);
   int v1 = ppc_allocate_vec_register(gen->f);
   int v2 = ppc_allocate_vec_register(gen->f);
   uint chan_index;
   boolean complement = FALSE;
   int one_vec = gen_one_vec(gen);

   FOR_EACH_DST0_ENABLED_CHANNEL(*inst, chan_index) {
      FETCH(gen, *inst, v0, 0, chan_index);   /* v0 = srcreg[0] */
      FETCH(gen, *inst, v1, 1, chan_index);   /* v1 = srcreg[1] */

      switch (inst->Instruction.Opcode) {
      case TGSI_OPCODE_SNE:
         complement = TRUE;
         /* fall-through */
      case TGSI_OPCODE_SEQ:
         ppc_vcmpeqfpx(gen->f, v2, v0, v1); /* v2 = v0 == v1 ? ~0 : 0 */
         break;

      case TGSI_OPCODE_SGE:
         complement = TRUE;
         /* fall-through */
      case TGSI_OPCODE_SLT:
         ppc_vcmpgtfpx(gen->f, v2, v1, v0); /* v2 = v1 > v0 ? ~0 : 0 */
         break;

      case TGSI_OPCODE_SLE:
         complement = TRUE;
         /* fall-through */
      case TGSI_OPCODE_SGT:
         ppc_vcmpgtfpx(gen->f, v2, v0, v1); /* v2 = v0 > v1 ? ~0 : 0 */
         break;
      default:
         assert(0);
      }

      /* v2 is now {0,0,0,0} or {~0,~0,~0,~0} */

      if (complement)
         ppc_vandc(gen->f, v2, one_vec, v2);    /* v2 = one_vec & ~v2 */
      else
         ppc_vand(gen->f, v2, one_vec, v2);     /* v2 = one_vec & v2 */

      STORE(gen, *inst, v2, 0, chan_index);   /* store v2 */
   }

   ppc_release_vec_register(gen->f, v0);
   ppc_release_vec_register(gen->f, v1);
   ppc_release_vec_register(gen->f, v2);
}


static void
emit_dotprod(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int v0 = ppc_allocate_vec_register(gen->f);
   int v1 = ppc_allocate_vec_register(gen->f);
   int v2 = ppc_allocate_vec_register(gen->f);
   uint chan_index;

   ppc_vxor(gen->f, v2, v2, v2);           /* v2 = {0, 0, 0, 0} */

   FETCH(gen, *inst, v0, 0, CHAN_X);       /* v0 = src0.XXXX */
   FETCH(gen, *inst, v1, 1, CHAN_X);       /* v1 = src1.XXXX */
   ppc_vmaddfp(gen->f, v2, v0, v1, v2);    /* v2 = v0 * v1 + v2 */

   FETCH(gen, *inst, v0, 0, CHAN_Y);       /* v0 = src0.YYYY */
   FETCH(gen, *inst, v1, 1, CHAN_Y);       /* v1 = src1.YYYY */
   ppc_vmaddfp(gen->f, v2, v0, v1, v2);    /* v2 = v0 * v1 + v2 */

   FETCH(gen, *inst, v0, 0, CHAN_Z);       /* v0 = src0.ZZZZ */
   FETCH(gen, *inst, v1, 1, CHAN_Z);       /* v1 = src1.ZZZZ */
   ppc_vmaddfp(gen->f, v2, v0, v1, v2);    /* v2 = v0 * v1 + v2 */

   if (inst->Instruction.Opcode == TGSI_OPCODE_DP4) {
      FETCH(gen, *inst, v0, 0, CHAN_W);    /* v0 = src0.WWWW */
      FETCH(gen, *inst, v1, 1, CHAN_W);    /* v1 = src1.WWWW */
      ppc_vmaddfp(gen->f, v2, v0, v1, v2); /* v2 = v0 * v1 + v2 */
   }
   else if (inst->Instruction.Opcode == TGSI_OPCODE_DPH) {
      FETCH(gen, *inst, v1, 1, CHAN_W);    /* v1 = src1.WWWW */
      ppc_vaddfp(gen->f, v2, v2, v1);      /* v2 = v2 + v1 */
   }

   FOR_EACH_DST0_ENABLED_CHANNEL(*inst, chan_index) {
      STORE(gen, *inst, v2, 0, chan_index);  /* store v2 */
   }
   ppc_release_vec_register(gen->f, v0);
   ppc_release_vec_register(gen->f, v1);
   ppc_release_vec_register(gen->f, v2);
}


static void
emit_triop(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int v0 = ppc_allocate_vec_register(gen->f);
   int v1 = ppc_allocate_vec_register(gen->f);
   int v2 = ppc_allocate_vec_register(gen->f);
   int v3 = ppc_allocate_vec_register(gen->f);
   uint chan_index;
   FOR_EACH_DST0_ENABLED_CHANNEL(*inst, chan_index) {
      FETCH(gen, *inst, v0, 0, chan_index);   /* v0 = srcreg[0] */
      FETCH(gen, *inst, v1, 1, chan_index);   /* v1 = srcreg[1] */
      FETCH(gen, *inst, v2, 2, chan_index);   /* v2 = srcreg[2] */
      switch (inst->Instruction.Opcode) {
      case TGSI_OPCODE_MAD:
         ppc_vmaddfp(gen->f, v3, v0, v1, v2);   /* v3 = v0 * v1 + v2 */
         break;
      case TGSI_OPCODE_LRP:
         ppc_vsubfp(gen->f, v3, v1, v2);        /* v3 = v1 - v2 */
         ppc_vmaddfp(gen->f, v3, v0, v3, v2);   /* v3 = v0 * v3 + v2 */
         break;
      default:
         assert(0);
      }
      STORE(gen, *inst, v3, 0, chan_index);   /* store v3 */
   }
   ppc_release_vec_register(gen->f, v0);
   ppc_release_vec_register(gen->f, v1);
   ppc_release_vec_register(gen->f, v2);
   ppc_release_vec_register(gen->f, v3);
}



/** Approximation for vr = pow(va, vb) */
static void
ppc_vec_pow(struct ppc_function *f, int vr, int va, int vb)
{
   /* pow(a,b) ~= exp2(log2(a) * b) */
   int t_vec = ppc_allocate_vec_register(f);
   int zero_vec = ppc_allocate_vec_register(f);

   ppc_vload_float(f, zero_vec, 0.0f);

   ppc_vlogefp(f, t_vec, va);                   /* t = log2(va) */
   ppc_vmaddfp(f, t_vec, t_vec, vb, zero_vec);  /* t = t * vb */
   ppc_vexptefp(f, vr, t_vec);                  /* vr = 2^t */

   ppc_release_vec_register(f, t_vec);
   ppc_release_vec_register(f, zero_vec);
}


static void
emit_lit(struct gen_context *gen, struct tgsi_full_instruction *inst)
{
   int one_vec = gen_one_vec(gen);

   /* Compute X */
   if (IS_DST0_CHANNEL_ENABLED(*inst, CHAN_X)) {
      STORE(gen, *inst, one_vec, 0, CHAN_X);
   }

   /* Compute Y, Z */
   if (IS_DST0_CHANNEL_ENABLED(*inst, CHAN_Y) ||
       IS_DST0_CHANNEL_ENABLED(*inst, CHAN_Z)) {
      int x_vec = ppc_allocate_vec_register(gen->f);
      int zero_vec = ppc_allocate_vec_register(gen->f);

      FETCH(gen, *inst, x_vec, 0, CHAN_X);        /* x_vec = src[0].x */

      ppc_vload_float(gen->f, zero_vec, 0.0f);    /* zero = {0,0,0,0} */
      ppc_vmaxfp(gen->f, x_vec, x_vec, zero_vec); /* x_vec = max(x_vec, 0) */

      if (IS_DST0_CHANNEL_ENABLED(*inst, CHAN_Y)) {
         STORE(gen, *inst, x_vec, 0, CHAN_Y);        /* store Y */
      }

      if (IS_DST0_CHANNEL_ENABLED(*inst, CHAN_Z)) {
         int y_vec = ppc_allocate_vec_register(gen->f);
         int z_vec = ppc_allocate_vec_register(gen->f);
         int w_vec = ppc_allocate_vec_register(gen->f);
         int pow_vec = ppc_allocate_vec_register(gen->f);
         int pos_vec = ppc_allocate_vec_register(gen->f);
         int c128_vec = ppc_allocate_vec_register(gen->f);

         FETCH(gen, *inst, y_vec, 0, CHAN_Y);        /* y_vec = src[0].y */
         ppc_vmaxfp(gen->f, y_vec, y_vec, zero_vec); /* y_vec = max(y_vec, 0) */

         FETCH(gen, *inst, w_vec, 0, CHAN_W);        /* w_vec = src[0].w */

         /* XXX clamp Y to [-128, 128] */
         ppc_vload_float(gen->f, c128_vec, 128.0f);

         /* if temp.x > 0
          *    pow(tmp.y, tmp.w)
          * else
          *   0.0
          */

         ppc_vec_pow(gen->f, pow_vec, y_vec, w_vec);      /* pow = pow(y, w) */
         ppc_vcmpgtfpx(gen->f, pos_vec, x_vec, zero_vec); /* pos = x > 0 */
         ppc_vand(gen->f, z_vec, pow_vec, pos_vec);       /* z = pow & pos */

         STORE(gen, *inst, z_vec, 0, CHAN_Z);             /* store Z */

         ppc_release_vec_register(gen->f, y_vec);
         ppc_release_vec_register(gen->f, z_vec);
         ppc_release_vec_register(gen->f, w_vec);
         ppc_release_vec_register(gen->f, pow_vec);
         ppc_release_vec_register(gen->f, pos_vec);
      }

      ppc_release_vec_register(gen->f, x_vec);
      ppc_release_vec_register(gen->f, zero_vec);
   }

   /* Compute W */
   if (IS_DST0_CHANNEL_ENABLED(*inst, CHAN_W)) {
      STORE(gen, *inst, one_vec, 0, CHAN_W);
   }
}


static int
emit_instruction(struct gen_context *gen,
                 struct tgsi_full_instruction *inst)
{
   switch (inst->Instruction.Opcode) {
   case TGSI_OPCODE_MOV:
   case TGSI_OPCODE_ABS:
   case TGSI_OPCODE_FLOOR:
   case TGSI_OPCODE_FRAC:
   case TGSI_OPCODE_EXPBASE2:
   case TGSI_OPCODE_LOGBASE2:
      emit_unaryop(gen, inst);
      break;
   case TGSI_OPCODE_RSQ:
   case TGSI_OPCODE_RCP:
      emit_scalar_unaryop(gen, inst);
      break;
   case TGSI_OPCODE_ADD:
   case TGSI_OPCODE_SUB:
   case TGSI_OPCODE_MUL:
   case TGSI_OPCODE_MIN:
   case TGSI_OPCODE_MAX:
      emit_binop(gen, inst);
      break;
   case TGSI_OPCODE_SEQ:
   case TGSI_OPCODE_SNE:
   case TGSI_OPCODE_SLT:
   case TGSI_OPCODE_SGT:
   case TGSI_OPCODE_SLE:
   case TGSI_OPCODE_SGE:
      emit_inequality(gen, inst);
      break;
   case TGSI_OPCODE_MAD:
   case TGSI_OPCODE_LRP:
      emit_triop(gen, inst);
      break;
   case TGSI_OPCODE_DP3:
   case TGSI_OPCODE_DP4:
   case TGSI_OPCODE_DPH:
      emit_dotprod(gen, inst);
      break;
   case TGSI_OPCODE_LIT:
      emit_lit(gen, inst);
      break;
   case TGSI_OPCODE_END:
      /* normal end */
      return 1;
   default:
      return 0;
   }

   
   return 1;
}

static void
emit_declaration(
   struct ppc_function *func,
   struct tgsi_full_declaration *decl )
{
   if( decl->Declaration.File == TGSI_FILE_INPUT ) {
#if 0
      unsigned first, last, mask;
      unsigned i, j;

      first = decl->DeclarationRange.First;
      last = decl->DeclarationRange.Last;
      mask = decl->Declaration.UsageMask;

      for( i = first; i <= last; i++ ) {
         for( j = 0; j < NUM_CHANNELS; j++ ) {
            if( mask & (1 << j) ) {
               switch( decl->Declaration.Interpolate ) {
               case TGSI_INTERPOLATE_CONSTANT:
                  emit_coef_a0( func, 0, i, j );
                  emit_inputs( func, 0, i, j );
                  break;

               case TGSI_INTERPOLATE_LINEAR:
                  emit_tempf( func, 0, 0, TGSI_SWIZZLE_X );
                  emit_coef_dadx( func, 1, i, j );
                  emit_tempf( func, 2, 0, TGSI_SWIZZLE_Y );
                  emit_coef_dady( func, 3, i, j );
                  emit_mul( func, 0, 1 );    /* x * dadx */
                  emit_coef_a0( func, 4, i, j );
                  emit_mul( func, 2, 3 );    /* y * dady */
                  emit_add( func, 0, 4 );    /* x * dadx + a0 */
                  emit_add( func, 0, 2 );    /* x * dadx + y * dady + a0 */
                  emit_inputs( func, 0, i, j );
                  break;

               case TGSI_INTERPOLATE_PERSPECTIVE:
                  emit_tempf( func, 0, 0, TGSI_SWIZZLE_X );
                  emit_coef_dadx( func, 1, i, j );
                  emit_tempf( func, 2, 0, TGSI_SWIZZLE_Y );
                  emit_coef_dady( func, 3, i, j );
                  emit_mul( func, 0, 1 );    /* x * dadx */
                  emit_tempf( func, 4, 0, TGSI_SWIZZLE_W );
                  emit_coef_a0( func, 5, i, j );
                  emit_rcp( func, 4, 4 );    /* 1.0 / w */
                  emit_mul( func, 2, 3 );    /* y * dady */
                  emit_add( func, 0, 5 );    /* x * dadx + a0 */
                  emit_add( func, 0, 2 );    /* x * dadx + y * dady + a0 */
                  emit_mul( func, 0, 4 );    /* (x * dadx + y * dady + a0) / w */
                  emit_inputs( func, 0, i, j );
                  break;

               default:
                  assert( 0 );
		  break;
               }
            }
         }
      }
#endif
   }
}



static void
emit_prologue(struct ppc_function *func)
{
   /* XXX set up stack frame */
}


static void
emit_epilogue(struct ppc_function *func)
{
   ppc_return(func);
   /* XXX restore prev stack frame */
}



/**
 * Translate a TGSI vertex/fragment shader to PPC code.
 *
 * \param tokens  the TGSI input shader
 * \param func  the output PPC code/function
 * \param immediates  buffer to place immediates, later passed to PPC func
 * \return TRUE for success, FALSE if translation failed
 */
boolean
tgsi_emit_ppc(const struct tgsi_token *tokens,
              struct ppc_function *func,
              float (*immediates)[4],
              boolean do_swizzles )
{
   static int use_ppc_asm = -1;
   struct tgsi_parse_context parse;
   /*boolean instruction_phase = FALSE;*/
   unsigned ok = 1;
   uint num_immediates = 0;
   struct gen_context gen;

   if (use_ppc_asm < 0) {
      /* If GALLIUM_NOPPC is set, don't use PPC codegen */
      use_ppc_asm = !debug_get_bool_option("GALLIUM_NOPPC", FALSE);
   }
   if (!use_ppc_asm)
      return FALSE;

   util_init_math();

   gen.f = func;
   gen.inputs_reg = ppc_reserve_register(func, 3);   /* first function param */
   gen.outputs_reg = ppc_reserve_register(func, 4);  /* second function param */
   gen.temps_reg = ppc_reserve_register(func, 5);    /* ... */
   gen.immed_reg = ppc_reserve_register(func, 6);
   gen.const_reg = ppc_reserve_register(func, 7);
   gen.one_vec = -1;
   gen.bit31_vec = -1;

   emit_prologue(func);

   tgsi_parse_init( &parse, tokens );

   while (!tgsi_parse_end_of_tokens(&parse) && ok) {
      tgsi_parse_token(&parse);

      switch (parse.FullToken.Token.Type) {
      case TGSI_TOKEN_TYPE_DECLARATION:
         if (parse.FullHeader.Processor.Processor == TGSI_PROCESSOR_FRAGMENT) {
            emit_declaration(func, &parse.FullToken.FullDeclaration );
         }
         break;

      case TGSI_TOKEN_TYPE_INSTRUCTION:
         ok = emit_instruction(&gen, &parse.FullToken.FullInstruction);

	 if (!ok) {
	    debug_printf("failed to translate tgsi opcode %d to PPC (%s)\n", 
			 parse.FullToken.FullInstruction.Instruction.Opcode,
                         parse.FullHeader.Processor.Processor == TGSI_PROCESSOR_VERTEX ?
                         "vertex shader" : "fragment shader");
	 }
         break;

      case TGSI_TOKEN_TYPE_IMMEDIATE:
         /* splat each immediate component into a float[4] vector for SoA */
         {
            const uint size = parse.FullToken.FullImmediate.Immediate.Size - 1;
            float *imm = (float *) immediates;
            uint i;
            assert(size <= 4);
            assert(num_immediates < TGSI_EXEC_NUM_IMMEDIATES);
            for (i = 0; i < size; i++) {
               const float value =
                  parse.FullToken.FullImmediate.u.ImmediateFloat32[i].Float;
               imm[num_immediates * 4 + 0] = 
               imm[num_immediates * 4 + 1] = 
               imm[num_immediates * 4 + 2] = 
               imm[num_immediates * 4 + 3] = value;
               num_immediates++;
            }
         }
         break;

      default:
	 ok = 0;
         assert( 0 );
      }
   }

   emit_epilogue(func);

   tgsi_parse_free( &parse );

   return ok;
}

#endif /* PIPE_ARCH_PPC */