summaryrefslogtreecommitdiffstats
path: root/src/amd/common/ac_surface.h
blob: 582a67193f8f79d50a0aed0e3cb45825c0510e2a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
/*
 * Copyright © 2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 */

#ifndef AC_SURFACE_H
#define AC_SURFACE_H

#include <stdint.h>

#include "amd_family.h"

#ifdef __cplusplus
extern "C" {
#endif

/* Forward declarations. */
typedef void* ADDR_HANDLE;

struct amdgpu_gpu_info;
struct radeon_info;

#define RADEON_SURF_MAX_LEVELS                  15

enum radeon_surf_mode {
    RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
    RADEON_SURF_MODE_1D = 2,
    RADEON_SURF_MODE_2D = 3,
};

/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
enum radeon_micro_mode {
    RADEON_MICRO_MODE_DISPLAY = 0,
    RADEON_MICRO_MODE_THIN = 1,
    RADEON_MICRO_MODE_DEPTH = 2,
    RADEON_MICRO_MODE_ROTATED = 3,
};

/* the first 16 bits are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_SCANOUT                     (1 << 16)
#define RADEON_SURF_ZBUFFER                     (1 << 17)
#define RADEON_SURF_SBUFFER                     (1 << 18)
#define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
#define RADEON_SURF_FMASK                       (1 << 21)
#define RADEON_SURF_DISABLE_DCC                 (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
#define RADEON_SURF_IMPORTED                    (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)

struct legacy_surf_level {
    uint64_t                    offset;
    uint64_t                    slice_size;
    uint64_t                    dcc_offset;
    uint64_t                    dcc_fast_clear_size;
    uint16_t                    nblk_x;
    uint16_t                    nblk_y;
    enum radeon_surf_mode       mode;
};

struct legacy_surf_layout {
    unsigned                    bankw:4;  /* max 8 */
    unsigned                    bankh:4;  /* max 8 */
    unsigned                    mtilea:4; /* max 8 */
    unsigned                    tile_split:13;         /* max 4K */
    unsigned                    stencil_tile_split:13; /* max 4K */
    unsigned                    pipe_config:5;      /* max 17 */
    unsigned                    num_banks:5;        /* max 16 */
    unsigned                    macro_tile_index:4; /* max 15 */

    /* Whether the depth miptree or stencil miptree as used by the DB are
     * adjusted from their TC compatible form to ensure depth/stencil
     * compatibility. If either is true, the corresponding plane cannot be
     * sampled from.
     */
    unsigned                    depth_adjusted:1;
    unsigned                    stencil_adjusted:1;

    struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
    struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
    uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
    uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
};

/* Same as addrlib - AddrResourceType. */
enum gfx9_resource_type {
    RADEON_RESOURCE_1D = 0,
    RADEON_RESOURCE_2D,
    RADEON_RESOURCE_3D,
};

struct gfx9_surf_flags {
    uint16_t                    swizzle_mode; /* tile mode */
    uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
};

struct gfx9_surf_meta_flags {
    unsigned                    rb_aligned:1;   /* optimal for RBs */
    unsigned                    pipe_aligned:1; /* optimal for TC */
};

struct gfx9_surf_layout {
    struct gfx9_surf_flags      surf;    /* color or depth surface */
    struct gfx9_surf_flags      fmask;   /* not added to surf_size */
    struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */

    struct gfx9_surf_meta_flags dcc;   /* metadata of color */
    struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
    struct gfx9_surf_meta_flags cmask; /* metadata of fmask */

    enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
    uint64_t                    surf_offset; /* 0 unless imported with an offset */
    /* The size of the 2D plane containing all mipmap levels. */
    uint64_t                    surf_slice_size;
    uint16_t                    surf_pitch; /* in blocks */
    uint16_t                    surf_height;
    /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
    uint32_t                    offset[RADEON_SURF_MAX_LEVELS];

    uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */

    uint64_t                    stencil_offset; /* separate stencil */
    uint64_t                    fmask_size;
    uint64_t                    cmask_size;

    uint32_t                    fmask_alignment;
    uint32_t                    cmask_alignment;
};

struct radeon_surf {
    /* Format properties. */
    unsigned                    blk_w:4;
    unsigned                    blk_h:4;
    unsigned                    bpe:5;
    /* Number of mipmap levels where DCC is enabled starting from level 0.
     * Non-zero levels may be disabled due to alignment constraints, but not
     * the first level.
     */
    unsigned                    num_dcc_levels:4;
    unsigned                    is_linear:1;
    /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
    unsigned                    micro_tile_mode:3;
    uint32_t                    flags;

    /* These are return values. Some of them can be set by the caller, but
     * they will be treated as hints (e.g. bankw, bankh) and might be
     * changed by the calculator.
     */
    uint64_t                    surf_size;
    uint64_t                    dcc_size;
    uint64_t                    htile_size;

    uint32_t                    htile_slice_size;

    uint32_t                    surf_alignment;
    uint32_t                    dcc_alignment;
    uint32_t                    htile_alignment;

    union {
        /* R600-VI return values.
         *
         * Some of them can be set by the caller if certain parameters are
         * desirable. The allocator will try to obey them.
         */
        struct legacy_surf_layout legacy;

        /* GFX9+ return values. */
        struct gfx9_surf_layout gfx9;
    } u;
};

struct ac_surf_info {
	uint32_t width;
	uint32_t height;
	uint32_t depth;
	uint8_t samples;
	uint8_t levels;
	uint16_t array_size;
};

struct ac_surf_config {
	struct ac_surf_info info;
	unsigned is_3d : 1;
	unsigned is_cube : 1;
};

ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
			       const struct amdgpu_gpu_info *amdinfo);

int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
		       const struct ac_surf_config * config,
		       enum radeon_surf_mode mode,
		       struct radeon_surf *surf);

#ifdef __cplusplus
}
#endif

#endif /* AC_SURFACE_H */