/* * Copyright © 2015 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ static uint32_t vertex_element_comp_control(enum isl_format format, unsigned comp) { uint8_t bits; switch (comp) { case 0: bits = isl_format_layouts[format].channels.r.bits; break; case 1: bits = isl_format_layouts[format].channels.g.bits; break; case 2: bits = isl_format_layouts[format].channels.b.bits; break; case 3: bits = isl_format_layouts[format].channels.a.bits; break; default: unreachable("Invalid component"); } if (bits) { return VFCOMP_STORE_SRC; } else if (comp < 3) { return VFCOMP_STORE_0; } else if (isl_format_layouts[format].channels.r.type == ISL_UINT || isl_format_layouts[format].channels.r.type == ISL_SINT) { assert(comp == 3); return VFCOMP_STORE_1_INT; } else { assert(comp == 3); return VFCOMP_STORE_1_FP; } } static void emit_vertex_input(struct anv_pipeline *pipeline, const VkPipelineVertexInputStateCreateInfo *info, const struct anv_graphics_pipeline_create_info *extra) { uint32_t elements; if (extra && extra->disable_vs) { /* If the VS is disabled, just assume the user knows what they're * doing and apply the layout blindly. This can only come from * meta, so this *should* be safe. */ elements = 0; for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) elements |= (1 << info->pVertexAttributeDescriptions[i].location); } else { /* Pull inputs_read out of the VS prog data */ uint64_t inputs_read = pipeline->vs_prog_data.inputs_read; assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0); elements = inputs_read >> VERT_ATTRIB_GENERIC0; } #if ANV_GEN >= 8 /* On BDW+, we only need to allocate space for base ids. Setting up * the actual vertex and instance id is a separate packet. */ const bool needs_svgs_elem = pipeline->vs_prog_data.uses_basevertex || pipeline->vs_prog_data.uses_baseinstance; #else /* On Haswell and prior, vertex and instance id are created by using the * ComponentControl fields, so we need an element for any of them. */ const bool needs_svgs_elem = pipeline->vs_prog_data.uses_vertexid || pipeline->vs_prog_data.uses_instanceid || pipeline->vs_prog_data.uses_basevertex || pipeline->vs_prog_data.uses_baseinstance; #endif uint32_t elem_count = __builtin_popcount(elements) + needs_svgs_elem; if (elem_count == 0) return; uint32_t *p; const uint32_t num_dwords = 1 + elem_count * 2; p = anv_batch_emitn(&pipeline->batch, num_dwords, GENX(3DSTATE_VERTEX_ELEMENTS)); memset(p + 1, 0, (num_dwords - 1) * 4); for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) { const VkVertexInputAttributeDescription *desc = &info->pVertexAttributeDescriptions[i]; enum isl_format format = anv_get_isl_format(desc->format, VK_IMAGE_ASPECT_COLOR_BIT, VK_IMAGE_TILING_LINEAR, NULL); assert(desc->binding < 32); if ((elements & (1 << desc->location)) == 0) continue; /* Binding unused */ uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1)); struct GENX(VERTEX_ELEMENT_STATE) element = { .VertexBufferIndex = desc->binding, .Valid = true, .SourceElementFormat = format, .EdgeFlagEnable = false, .SourceElementOffset = desc->offset, .Component0Control = vertex_element_comp_control(format, 0), .Component1Control = vertex_element_comp_control(format, 1), .Component2Control = vertex_element_comp_control(format, 2), .Component3Control = vertex_element_comp_control(format, 3), }; GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element); #if ANV_GEN >= 8 /* On Broadwell and later, we have a separate VF_INSTANCING packet * that controls instancing. On Haswell and prior, that's part of * VERTEX_BUFFER_STATE which we emit later. */ anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), .InstancingEnable = pipeline->instancing_enable[desc->binding], .VertexElementIndex = slot, /* Vulkan so far doesn't have an instance divisor, so * this is always 1 (ignored if not instancing). */ .InstanceDataStepRate = 1); #endif } const uint32_t id_slot = __builtin_popcount(elements); if (needs_svgs_elem) { /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum: * "Within a VERTEX_ELEMENT_STATE structure, if a Component * Control field is set to something other than VFCOMP_STORE_SRC, * no higher-numbered Component Control fields may be set to * VFCOMP_STORE_SRC" * * This means, that if we have BaseInstance, we need BaseVertex as * well. Just do all or nothing. */ uint32_t base_ctrl = (pipeline->vs_prog_data.uses_basevertex || pipeline->vs_prog_data.uses_baseinstance) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0; struct GENX(VERTEX_ELEMENT_STATE) element = { .VertexBufferIndex = 32, /* Reserved for this */ .Valid = true, .SourceElementFormat = ISL_FORMAT_R32G32_UINT, .Component0Control = base_ctrl, .Component1Control = base_ctrl, #if ANV_GEN >= 8 .Component2Control = VFCOMP_STORE_0, .Component3Control = VFCOMP_STORE_0, #else .Component2Control = VFCOMP_STORE_VID, .Component3Control = VFCOMP_STORE_IID, #endif }; GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element); } #if ANV_GEN >= 8 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid, .VertexIDComponentNumber = 2, .VertexIDElementOffset = id_slot, .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid, .InstanceIDComponentNumber = 3, .InstanceIDElementOffset = id_slot); #endif } static inline void emit_urb_setup(struct anv_pipeline *pipeline) { #if ANV_GEN == 7 struct anv_device *device = pipeline->device; /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: * * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS, * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS, * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL * needs to be sent before any combination of VS associated 3DSTATE." */ anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL, .DepthStallEnable = true, .PostSyncOperation = WriteImmediateData, .Address = { &device->workaround_bo, 0 }); #endif anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), .ConstantBufferOffset = 0, .ConstantBufferSize = 4); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS), .ConstantBufferOffset = 4, .ConstantBufferSize = 4); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), .ConstantBufferOffset = 8, .ConstantBufferSize = 4); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS), .VSURBStartingAddress = pipeline->urb.vs_start, .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1, .VSNumberofURBEntries = pipeline->urb.nr_vs_entries); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_GS), .GSURBStartingAddress = pipeline->urb.gs_start, .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1, .GSNumberofURBEntries = pipeline->urb.nr_gs_entries); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_HS), .HSURBStartingAddress = pipeline->urb.vs_start, .HSURBEntryAllocationSize = 0, .HSNumberofURBEntries = 0); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_DS), .DSURBStartingAddress = pipeline->urb.vs_start, .DSURBEntryAllocationSize = 0, .DSNumberofURBEntries = 0); } static inline uint32_t scratch_space(const struct brw_stage_prog_data *prog_data) { return ffs(prog_data->total_scratch / 2048); } static const uint32_t vk_to_gen_cullmode[] = { [VK_CULL_MODE_NONE] = CULLMODE_NONE, [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT, [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK, [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH }; static const uint32_t vk_to_gen_fillmode[] = { [VK_POLYGON_MODE_FILL] = FILL_MODE_SOLID, [VK_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME, [VK_POLYGON_MODE_POINT] = FILL_MODE_POINT, }; static const uint32_t vk_to_gen_front_face[] = { [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1, [VK_FRONT_FACE_CLOCKWISE] = 0 }; static const uint32_t vk_to_gen_logic_op[] = { [VK_LOGIC_OP_COPY] = LOGICOP_COPY, [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR, [VK_LOGIC_OP_AND] = LOGICOP_AND, [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE, [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED, [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP, [VK_LOGIC_OP_XOR] = LOGICOP_XOR, [VK_LOGIC_OP_OR] = LOGICOP_OR, [VK_LOGIC_OP_NOR] = LOGICOP_NOR, [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV, [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT, [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE, [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED, [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED, [VK_LOGIC_OP_NAND] = LOGICOP_NAND, [VK_LOGIC_OP_SET] = LOGICOP_SET, }; static const uint32_t vk_to_gen_blend[] = { [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO, [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE, [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR, [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR, [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR, [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR, [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA, [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA, [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA, [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA, [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR, [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR, [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA, [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA, [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE, [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR, [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR, [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA, [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA, }; static const uint32_t vk_to_gen_blend_op[] = { [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD, [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT, [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT, [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN, [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX, }; static const uint32_t vk_to_gen_compare_op[] = { [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER, [VK_COMPARE_OP_LESS] = PREFILTEROPLESS, [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL, [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL, [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER, [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL, [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL, [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS, }; static const uint32_t vk_to_gen_stencil_op[] = { [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP, [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO, [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE, [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT, [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT, [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT, [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR, [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR, };