# Copyright (C) 2016 Intel Corporation. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS # IN THE SOFTWARE. # # Provides definitions for events. enum AR_DRAW_TYPE { Instanced = 0, IndexedInstanced = 1, InstancedSplit = 2, IndexedInstancedSplit = 3 }; event Framework::ThreadStartApiEvent { }; event Framework::ThreadStartWorkerEvent { }; event SwrApi::DrawInfoEvent { uint32_t drawId; AR_DRAW_TYPE type; uint32_t topology; uint32_t numVertices; uint32_t numIndices; int32_t indexOffset; int32_t baseVertex; uint32_t numInstances; uint32_t startInstance; uint32_t tsEnable; uint32_t gsEnable; uint32_t soEnable; uint32_t soTopology; uint32_t splitId; // Split draw count or id. }; event SwrApi::DispatchEvent { uint32_t drawId; uint32_t threadGroupCountX; uint32_t threadGroupCountY; uint32_t threadGroupCountZ; }; event SwrApi::FrameEndEvent { uint32_t frameId; uint32_t nextDrawId; }; ///@brief API Stat: Synchonization event. event SwrApi::SwrSyncEvent { uint32_t drawId; }; ///@brief API Stat: Invalidate hot tiles (i.e. tile cache) event SwrApi::SwrInvalidateTilesEvent { uint32_t drawId; }; ///@brief API Stat: Invalidate and discard hot tiles within pixel region event SwrApi::SwrDiscardRectEvent { uint32_t drawId; }; ///@brief API Stat: Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache) event SwrApi::SwrStoreTilesEvent { uint32_t drawId; }; event Pipeline::FrontendStatsEvent { uint32_t drawId; uint64_t counter IaVertices; uint64_t counter IaPrimitives; uint64_t counter VsInvocations; uint64_t counter HsInvocations; uint64_t counter DsInvocations; uint64_t counter GsInvocations; uint64_t counter GsPrimitives; uint64_t counter CInvocations; uint64_t counter CPrimitives; uint64_t counter SoPrimStorageNeeded0; uint64_t counter SoPrimStorageNeeded1; uint64_t counter SoPrimStorageNeeded2; uint64_t counter SoPrimStorageNeeded3; uint64_t counter SoNumPrimsWritten0; uint64_t counter SoNumPrimsWritten1; uint64_t counter SoNumPrimsWritten2; uint64_t counter SoNumPrimsWritten3; }; event Pipeline::BackendStatsEvent { uint32_t drawId; uint64_t counter DepthPassCount; uint64_t counter PsInvocations; uint64_t counter CsInvocations; }; event Pipeline::EarlyZSingleSample { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateZSingleSample { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyStencilSingleSample { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateStencilSingleSample { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyZSampleRate { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateZSampleRate { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyStencilSampleRate { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateStencilSampleRate { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; // Total Early-Z counts, SingleSample and SampleRate event Pipeline::EarlyZ { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; // Total LateZ counts, SingleSample and SampleRate event Pipeline::LateZ { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; // Total EarlyStencil counts, SingleSample and SampleRate event Pipeline::EarlyStencil { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; // Total LateStencil counts, SingleSample and SampleRate event Pipeline::LateStencil { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyZNullPS { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyStencilNullPS { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyZPixelRate { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateZPixelRate { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyOmZ { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::EarlyOmStencil { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateOmZ { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::LateOmStencil { uint32_t drawId; uint64_t counter passCount; uint64_t counter failCount; }; event Pipeline::GSInputPrims { uint32_t drawId; uint64_t counter inputPrimCount; }; event Pipeline::GSPrimsGen { uint32_t drawId; uint64_t counter primGeneratedCount; }; event Pipeline::GSVertsInput { uint32_t drawId; uint64_t counter vertsInput; }; event Pipeline::TessPrims { uint32_t drawId; uint64_t counter primCount; }; event Pipeline::RasterTiles { uint32_t drawId; uint32_t counter rastTileCount; }; event Pipeline::ClipperEvent { uint32_t drawId; uint32_t counter trivialRejectCount; uint32_t counter trivialAcceptCount; uint32_t counter mustClipCount; }; event Pipeline::CullEvent { uint32_t drawId; uint64_t counter backfacePrimCount; uint64_t counter degeneratePrimCount; }; event Pipeline::AlphaEvent { uint32_t drawId; uint32_t counter alphaTestCount; uint32_t counter alphaBlendCount; }; event Shader::VSInfo { uint32_t drawId; uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event Shader::HSInfo { uint32_t drawId; uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event Shader::DSInfo { uint32_t drawId; uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event Shader::GSInfo { uint32_t drawId; uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event Shader::PSInfo { uint32_t drawId; uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event Shader::CSInfo { uint32_t drawId; uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event SWTagApi::SWTagEndFrameEvent { uint64_t frameCount; uint32_t renderpassCount; uint32_t drawOrDispatchCount; uint32_t drawCount; uint32_t dispatchCount; }; event SWTagApi::SWTagRenderpassEvent { uint64_t frameCount; uint32_t renderpassCount; uint32_t drawOrDispatchCount; uint32_t drawCount; uint32_t dispatchCount; }; event SWTagApi::SWTagDrawEvent { uint64_t frameCount; uint32_t renderpassCount; uint32_t drawOrDispatchCount; uint32_t drawCount; uint32_t dispatchCount; }; event SWTagApi::SWTagDispatchEvent { uint64_t frameCount; uint32_t renderpassCount; uint32_t drawOrDispatchCount; uint32_t drawCount; uint32_t dispatchCount; }; event SWTagApi::SWTagDriverCallEvent { char cmd[256]; }; event SWTag::SWTagFlushEvent { uint32_t count; char reason[256]; uint32_t type; }; event Memory::MemoryStatsEvent { uint32_t drawId; uint64_t baseAddr; uint32_t accessCountRead; uint32_t accessCountWrite; uint32_t totalSizeRead; uint32_t totalSizeWrite; uint64_t tscMin; uint64_t tscMax; };